教授紹介


氏名 
藤田 昌宏  教授
生年月日 
1956月10月7日 
専攻名 
電気工学専攻 
講座名 
電気工学原論 



  
 
 
 
  1. 略歴
  1. 学歴
    期間  学校名 
    1976年4月-1980年3月  東京大学工学部電気工学科 
    1980年4月-1982年3月  東京大学工学系研究科情報工学専門課程(修士) 
    1982年4月-1985年3月  東京大学工学系研究科情報工学専門課程(博士)
  2. 職歴
    期間  勤務先  職務 
    1985年4月-1993年10月  株式会社富士通研究所  研究員 
    1993年11月-2000年2月  米国富士通研究所  CADグループディレクタ
  3. 学位
    取得年月  大学名  学位 
    1980年3月  東京大学工学部  工学学士 
    1982年3月  東京大学大学院工学系研究科  修士(工学) 
    1985年3月  東京大学大学院工学系研究科  博士(工学) 

 
 
  1. 研究業績
    1. 概括表
      1. 研究論文(original papersで学術雑誌などに発表されたもの)
        単著  筆頭著者である共著  その他の共著 
        和文  1篇(0篇)  4篇(0篇)  2篇(0篇) 
        英文  0篇(0篇)  6篇(1篇)  12篇(6篇) 
      2. 解説論文、総合報告など
        単著  筆頭著者である共著  その他の共著 
        和文  1篇(1篇)  5篇(1篇)  0篇(0篇) 
        英文  4篇(3篇)  4篇(4篇)  3篇(2篇) 
      3. 著書、編書
        単著  筆頭著者である共著  その他の共著 
        和文  0篇(0篇)  0篇(0篇)  0篇(0篇) 
        英文  0篇(0篇)  1篇(1篇)  1篇(1篇) 
      4. 国際会議
        単著  筆頭著者である共著  その他の共著 
        英文  3篇(1篇)  16篇(2篇)  47篇(31篇) 
      ()内は、最近5年間のもので内数
    2. 研究論文
      • M. Fujita, H. Tanaka, T. Moto-oka
        Temporal Logic based hardware description and its verification with Prolog
        New Generation Computing, Vol.1, No. 2, 1983.
      • 藤田、田中、元岡
        時相論理によるハードウェア仕様記述とPrologを用いたゲート回路の 検証
        情報処理学会論文誌、第25巻2号、1984 藤田、田中、元岡、”ハードウェア状態遷移表現のPrologによる検証”、情報処理学会論文誌、 第25巻4号、1984
      • 藤田、田中、元岡
        時相論理によるハードウェア同期部の仕様記述とPrologによるその状 態遷移表への自動合成法
        情報処理学会論文誌、第26巻1号、1985
      • M. Fujita, S. Kono, H. Tanaka, T. Moto-oka
        Aid to hierarchical andstructured logic design using temporal logic and Prolog
        Proceedings. Pt. E, pages 283-294, IEE, 1986.
      • 藤田
        トンランスダクション法に基づく多段論理回路簡単化機能をもつ論理合成システムと その評価
        情報処理学会論文誌、第30巻5号、1989年5月. 中村、藤田、河野、田中、”時相論理に基づく論理回路検証システム”、情報処理学会論文誌、 1989年6月
      • H. Sato, S. Yoshihide, M. Fujita
        Speed turnable finite state machine compiler: ZEPHCAD
        Fujitsu Scientific & Technical Journal, Vol. 25, No. 4, 1989.
      • M. Fujita, H. Fujisawa, N. Kawato
        Unified Hardware Description Language (UHDL) and Its Support Tools
        Fujitsu Scientific & Technical Journal, Vol. 26, No. 1, 1990.
      • 藤田, 藤沢, 松永, 角田
        2分決定グラフのための変数順決定アルゴリズムとその評価
        情報 処理学会論文誌, 第31巻, 4号, 1990.
      • 松永裕介, 藤田昌宏
        順序付き2分決定グラフと許容関数を用いた多段論理回路簡単化手 法
        電子情報通信学会論文誌, J74-A, No. 2, 1991.
      • Y. Kukimoto, M. Fujita
        Application of Boolean Unification to Combinational Logic Synthesis
        IEICE Trans. Fundamentals of Elect., Vol. E75, No. 10, 1992.
      • Y. Matsunaga, M. Fujita
        Enhanced Unique Sensitization for Efficient Test Generation
        IEICE Trans. Inf. & Syst., Vol. E76-D, No. 9, Sept. 1993.
      • K-C. Chen, M. Fujita
        Network Resynthesis Algorithms for Delay Minimization
        IEICE Trans. Inf. & Syst., Vol. E76-D, No. 9, Sept. 1993.
      • Y. Kukimoto, M. Fujita
        Timing Optimization of Multi-Level Networks Using Boolean Relations
        IEICE Trans. Fundamentals of Elect., Vol. E76, No. 3, 1993.
      • M. Fujita, H. Fujisawa, Y. Matsunaga
        Variable Ordering Algorithms for Ordered Binary Decision Diagrams and their Evaluation
        IEEE Trans. CAD, Vol. 12, No. 1, Jan. 1993.
      • M. Fujita, Y. Matsunaga
        Variable Ordering of Binary Decision Diagrams for Multi-Level Logic Minimization
        Fujitsu Scientific & Technical Journal, Vol. 29, No. 2, 1993.
      • Y. Matsunaga, M. Fujita
        A Fast Test Pattern Generation for Large Scale Circuits
        Fujitsu Scientific & Technical Journal, Vol. 29, No. 4, 1993.
      • J. Jain, R. Mukherjee, M. Fujita
        VERIFUL: VERIfication using FUnctional Learning
        Fujitsu Scientific & Technical Journal, Vol. 31, No. 2, 1995.
      • R. J. Carragher, C-K Cheng, X-M Xiong, M. Fujita, R. Paturi
        Solving the Net Matching Problem in High-Performance Chip Design
        Transactions on Computer-Aided Design of Integrated Circnuits and Systems, vol. 15, no. 8, pp. 902--911, 1996.
      • E. M. Clarke, K. McMillan, M. Fujita, J. Yang
        Spectral Transforms for Large Boolean Functions with application to Technology Mapping
        Formal Method in System Design, Vol. 10, No. 2/3, 1997, Kluwar Academic Publishers.
      • M. Fujita, P. McGeer, J. Yang
        Multi-Terminal Binary Decision Diagrams: An Efficient Date Structure for Matrix Representation
        Formal Method in System Design, Vol. 10, No. 2/3, 1997, Kluwar Academic Publishers.
      • M. T.-C. Lee, Y-C Hsu, B. Chen, M. Fujita
        Domain-Specific High-Level Modeling and Synthesis for ATM Switch Prototyping
        Design Automation for Embedded Systems, Vol. 2, No. 3/4, May 1997.
      • S. Rajan, Mike Lee, Ke Yuan, M. Fujita
        ATM Switch Design by High-Level Modeling, Formal Verification, and High-Level Synthesis
        ACM Transactions on Design Automation (TODAES), October 1998.
      • A. Sudarsanam, S. Malik, M. Fujita
        A Retargetable Compilation Methodology for Embedded Digital System Processors Using a Machine-Dependent Code Optimization Library
        Design Automation for Embedded Systems, Kluwer Academic Publishers, Vol. 4, No. 2/3, 1999.
    3. 解説論文、総合報告等
      • F. Maruyama, M. Fujita
        Hardware Verification
        IEEE Compueter, Feb. 1985.
      • M. Fujita
        Logic Design Assistance with Temporal Logic
        invited talk at IEEE International Symposium on Multiple Valued Logic, Spain, May 1989.
      • 藤田, E. M. Clarke
        二分決定グラフの設計検証、論理合成への応用
        第5回軽井沢回路 とシステムワークショップ, 1992年4月.
      • 藤田、松永
        形式的検証による実設計の検証例
        第6回軽井沢回路とシステムワークショ ップ, 1993年4月.
      • 藤田、佐藤
        BDD(2分決定グラフ)特集
        情報処理、1993年5月.
      • 藤田, Clarke
        BDDのCADへの応用
        情報処理, 1993年5月
      • 藤田、陳、山崎
        形式的検証手法の実設計への適用例
        情報処理、1994年.
      • M. Fujita
        Practical Techniques of Formal Verification
        IFIP WG10.2 Seminar on Formal Verification, India, Jan. 1996.
      • Edmund M. Clarke, Robert Kurshan, Ken McMillan, Masahiro Fujita
        Computer-Aided Verificaiotn
        IEEE Spectrum, June 1996.
      • L. Claesen, Y. Matsunaga, M. Fujita
        Practical Aspects of State-of-the-art Formal Verification Techniques
        half day tutorial at ICCD, Oct. 1996.
      • M. Fujita, E. Clarke, J. Abraham
        Practical Techniques of Formal Verification
        one day tutorial at ASPDAC97, Japan, Jan. 1997.
      • M. Fujita, R. Murgai
        Delay Estimation and Optimization of Logic Circuit: A Survey
        invited paper at ASPDAC97, Japan, Jan. 1997.
      • M. Fujita
        Binary Decision Diagrams and its extensions
        invited talk at International Workshop on Reed-Muller expansion circuits, Oxford, Sept. 1997.
      • M. Fujita
        Model Checking: Its Basics and Reality
        invited paper at ASPDAC98, Japan, Jan. 1998.
      • 藤田
        フォーマルベリフィケーションでできること、できないこと
        DesignWave、CQ 出版、1998年7月
      • M. Fujita, R. Murgai
        Delay Estimation and Optimization of Techology Independent Logic Circuit: A Survey
        invited paper at ASICON98, Beijing, China, Oct. 1998.
      • M. Fujita, S. Rajan, A. Hu
        Two real formal verification experiences: ATM switch chip and parallel cache protocol
        invited paper at Workshop on current trends in applied formal method, Boppard, Germany, 1998.
    4. 著書、編書
      • M. Fujita, V. Boppana
        Design verification and fault diagnosis in manufacturing
        In J. Webster ed. Wiley Encyclopedia of Electrical and Electronics Engineering, John Wiley & Son, 1999.
      • Tsutomu Sasao, Masahiro Fujita (edit)
        Representation of Descrete Functions
        1996, Kluwer Academic Publishers.
    5. 国際会議発表
      • M. Fujita, H. Tanaka T. Moto-oka
        Verification with Prolog and Temporal Logic
        Proc. of IFIP WG10.2 International Conference on Hardware Description Languages and their Applications, May, 1983
      • M. Fujita, H. Tanaka, T. Moto-oka
        Specifying Hardware in Temporal Logic and Efficient Synthesis of State-diagrams Using Prolog
        FGCS'84, Tokyo, November, 1984.
      • M. Fujita, H. Tanaka, T. Moto-oka
        Logic Design Assistance with Temporal Logic
        Proc. of IFIP WG10.2 International Conference on Hardware Description Languages and their Applications, Aug., 1985
      • T. Aoyagi, M. Fujita, H. Tanaka
        Temporal Logic Programming Language Tokio
        Proc. Logic Programming Conference, LNCS-221, Springer-Verlag, 1985
      • S. Kono, T. Aoyagi, M. Fujita, H. Tanaka
        Implementation of temporal logic programming language Tokio
        Proc. Logic Programming Conference, LNCS-221, Springer-Verlag, 1985
      • M. Fujita, S. Kono, H. Tanaka, T. Moto-oka
        Tokio: Logic Programming Language Based on Temporal Logic and Its Compilation to Prolog
        3rd ICLP, London, July 1986.
      • H. Nakamura, M. Fujita, S. Kono, H. Tanaka
        Temporal Logic Based Fast Verification systems Using Cover Expressions
        Proc. of IFIP WG10.5 International Conference on VLSI, Aug., 1987
      • M. Fujita, H. Fujisawa
        Specification, verificaiton, and synthesis of control circuits with propositional temporal logic
        Proc. of CHDL89, 1989.
      • M. Fujita, H. Fujisawa, N. Kawato
        Evaluation and improvements of a Boolean comparison method based on binary decision diagrams
        Proc. of ICCAD89, 1989.
      • M. Fujita, Y. Matsunaga, H. Fujisawa
        On the application of binary decision diagrams to formal hardware design
        IMEC-IFIP International workshop on applied formal methods for correct VLSI design, 1989.
      • H. Nakamura, M. Fujita, S. Kono, M. Nakai, H. Tanaka
        A data path verification system using tempral logic based languages: Tokio
        IFIP WG10.2 Working Conference on the CAD Systems using AI Techniques, Tokyo, June 1989.
      • Y. Matsunaga and M. Fujita
        Multi Level Logic Optimization Using Binary Decision Diagrams
        Proc. IEEE Int. Conf. on Computer-Aided Design (ICCAD--89), Nov., 1989
      • Y. Matsunaga, M. Fujita
        Multi-Level Logic Optimization Using Binary Decision Diagrams
        Synthesis and Simulation Meeting and International Interchange (SASIMI'89), April 1989.
      • H. Nakamura, Y. Kukimoto, M. Fujita, H. Tanaka
        A data path verifier for register transfer level using temporal logic language Tokio
        Proc. CAV90, 1990.
      • M. Fujita and T. Kakuda and Y. Matsunaga
        Redesign and automatic error correction of combinational circuits
        Proc. of IFIP Working Conference on Logic and Architectural Synthesis, May, 1990.
      • Y. Matsunaga, M. Fujita
        Multi-Level Logic Minimization across Latch Boundaries
        Proc. of ICCAD, 1990.
      • M. Fujita, Y. Matsunaga
        Multi-level Logic Minimization based on Minimal Support and its application to the Minimization of Look-up Table Type FPGAs", Boundaries
        Proc. of ICCAD, 1990.
      • M. Fujita, Y. Matsunaga, T. Kakuda
        On variable ordering of binary decision diagrams for the application of multi-level logic synthesis
        Proc. of EDAC-91, Mar., 1991.
      • M. Fujita and Y. Tamiya and Y. Kukimoto and K.C. Chen
        Application of Boolean Unification to Combinational Logic Synthesis
        Proceedings of IEEE ICCAD91, Nov., 1991.
      • K.C. Chen and Y. Matsunaga and S. Muroga and M. Fujita
        A Resynthesis Approach for Network Optimization
        Proc. of 28th DAC, Jun., 1991.
      • Y. Matsunaga, M. Fujita
        A fast pattern generation for large scale circuits
        Synthesis, Simulation Meeting and International Interchange (SASIMI'92), 1992.
      • K.C. Chen and M. Fujita
        Efficient Sum-To-One Subsets Algorithm for Logic Optimization
        Proc.of 29th DAC, Jun., 1992.
      • M. Fujita, Y. Matsunaga, Y. Tamiya, K.C. Chen
        Multi-Level Logic Minimization of Large Combinational Circuits by Partitioning
        International Symposium on Logic Synthesis and Microprocessor Architecture, July, 1992.
      • Y. Kukimoto and M. Fujita
        Rectification Method for Lookup-Table Type FPGA's
        Proc. of ICCAD-92, Nov., 1992.
      • M. Fujita
        RTL Design Verification by Making Use of Datapath Information
        Proc. of ICCD-92, Oct., 1992.
      • E.M. Clarke and K.L. McMillan and X. Zhao and M. Fujita and J. Yang
        Spectral Transforms for Large Boolean Functions with Application to Technology Mapping
        Proc. 30th ACM/IEEE Design Automation Conf., June, 1993
      • M. Fujita
        A Method for Automatic Design Error Correction in Sequential Circuits
        Proc. of EDAC-93, Feb. 1993.
      • M. Fujita and S. Kono
        Synthesis of controllers from Interval Temporal Logic specification
        Proc. International Conference on Computer Design (ICCD), Oct., 1993.
      • B. Chen and M. Yamazaki and M. Fujita
        Bug Identification of a Real Chip Design by Symbolic Model Checking
        Proc. of EDAC 94, Feb., 1994.
      • M. Fujita and J. Yang and E.M. Clarke and X. Zhao and P. McGeer
        Fast Spectrum Computation for Logic Functions using Binary Decision Diagrams
        Proc. of ISCAS 94, May, 1994
      • Y. Tamiya, Y. Matsunaga, M. Fujita
        LP based Cell Selection wth Constraints of Timing, Area, and Power Consumption
        ICCAD94, Nov. 1994.
      • Robert J. Carragher, Masahiro Fujita, and Chung-Kuan Cheng
        Simple Tree-Construction Heuristics for the Fanout Problem
        in Proc. of the 1995 International Conference on Computer Design, Austin, TX., October 1995, pp. 671-679.
      • Y. Kukimoto, M. Fujita, R. Brayton
        A Redesign Technique for Combinational Circuits Based on Gate Reconnections
        ICCAD94, Nov. 1994.
      • Jawahar Jain, Rajarshi Mukherjee, Masahiro Fujita
        VERIFUL:VERIfication using FUnctional Learning
        European Design and Test Conference, March 1995.
      • Jawahar Jain, Rajarshi Mukherjee, Masahiro Fujita
        Advanced Learning Based Verification Techniques
        Design Automation Conference, June 1995.
      • M. T.-C. Lee, V. Tiwari, S. Malik, and M. Fujita
        Power Analysis and Low-Power Scheduling Techniques for Embedded DSP Software
        Proc. IEEE Int'l Symp. on System Synthesis, Cannes, France, September 1995.
      • M. Fujita, B. Chen, M. Yamazaki
        A verification technique for communication hardware and its application to a real chip design
        Proc. of CICC95, 1995.
      • Robert Carragher, Masahiro Fujita
        Simple Tree-Construction Heuristics for the Fanout Problem
        ICCD95.
      • E. M. Clarke, M. Fujita, X. Zhao
        Hybrid Decision Diagrams
        ICCAD95, Nov. 1995.
      • Rajarshi Mukherjee, Jawahar Jain, Masahiro Fujita, Jacob A. Abraham, Donald S. Fussell
        On More Efficient Combinational ATPG using Functional Learning
        1996 VLSI Design.
      • Amit Narayan, Sunil P. Khatri, Jawahar Jain, Robert K. Brayton, Alberto Sangiovanni-Vincentelli, Masahiro Fujita
        A Study of Composition Schemes for Mixed Apply/Compose Based Construction of OBDDs
        1996 VLSI Design.
      • Masahiro Fujita, Yuji Kukimoto, Robert Brayton
        BDD minimization by truth table permutation
        ISCAS, May 1996.
      • Edmund M. Clarke, Masahiro Fujita, Xudong Zhao
        Application of Multi- Terminal Binary Decision Diagrams
        in Representation of Discrete Functions, 1996, Kluwer Academic Publishers.
      • Mike Lee, Y-C. Hsu, Ben Chen, Masahiro Fujita
        Domain-Specific High-Level Modeling and Synthesis for ATM Switch Design Using VHDL
        DAC, June, 1996.
      • Masahiro Fujita
        Verification of arithmetic circuits by comparing two similar circuits
        Computer Aided Verification, July 1996.
      • Jawahar Jain, Amit Narayan, Claudionor Coelho, Sunil P. Khatri, A. Sangiovanni-Vincentelli, Robert K. Brayton, Masahiro Fujita
        Decomposition Techniques for Efficient ROBDD Construction
        FMCAD, Nov. 1996.
      • Amit Narayan, Jawahar Jain, Masahiro Fujita, A. Sangiovanni-Vincentelli
        Partitioned ROBDDs - A Compact, Canonical and Efficient Manipulable Rep- resentation for Boolean Functions
        ICCAD, Nov. 1996.
      • Mike T-C. Lee, Yu-Chin Hsu, Ben Chen, Masahiro Fujita
        Domain-Specific High-Level Modeling and Synthesis for ATM Switch Design Using VHDL
        Proceedings of the 33th Design Automation Conference (DCA), June, 1996.
      • J. Jain, A. Narayan, M. Fujita and A. Sangiovanni-Vincentelli
        Formal Verification of Combinational Circuits
        10th International Conference on VLSI Design, Jan. 1997, Hyderabad, India.
      • J. Jain, A. Narayan, M. Fujita and A. Sangiovanni-Vincentelli
        A Survey of Combinational Verification Techniques
        International Conference on Computer Design, October 1997.
      • A. Hu and M. Fujita and C. Wilson
        Formal Verification of the HAL S1 System Cache Coherence Protocol
        Proc. of International Conference on Computere Design (ICCD), Oct., 1997.
      • Rajarshi Mukherjee, Jawahar Jain, Koichiro Takayama, Masahiro Fujita, Jacob Abraham, Don Fussell, Jacob Abraham
        Efficient Combinational Verification Using BDDs and a Hash Table
        1997 ACM/IEEE International Workshop on Logic Synthesis, May 1997.
      • Rajarshi Mukherjee, Jawahar Jain, Koichiro Takayama, Masahiro Fujita, Jacob Abraham, Don Fussell, Jacob Abraham
        FLOVER: Filtering Oriented Combinational Verification Approach
        1997 ACM/IEEE International Workshop on Logic Synthesis, May 1997.
      • Rajarshi Mukherjee, Jawahar Jain, Koichiro Takayama, Masahiro Fujita, Jacob Abraham, Don Fussell, Jacob Abraham
        Efficient Combinational Verification Using BDDs and a Hash Table
        ISCAS, June 1997.
      • S. Rajan, K. Yuan, M. T-C. Lee, and M. Fujita
        High-Level Design and Validation of ATM Switch
        High-Level Design, Validation, and Test (HLDVT), Oakland, November 1997.
      • S. Rajan, M. Fujita
        ATM Switch Design: Parametric High-Level Modeling and Formal Verification
        Algebraic Methodology and Software Technology (AMAST), Sydney, Australia, December 1997.
      • S. Rajan, M. Fujita
        Integration of High-Level Modeling, Formal Verification, and High-Level Synthesis in ATM Switch Design
        International Conference on VLSI Design (VLSI), Madras, India, January 1998.
      • Rajarshi Mukherjee, Jawahar Jain, Koichiro Takayama, Masahiro Fujita, Jacob Abraham, Don Fussell, Jacob Abraham
        Automatic Partitioning for Efficient Combinational Verification
        1998 ACM/IEEE International Workshop on Logic Synthesis, May 1998.
      • V. Boppana, M. Fujita
        Modeling the Unknown ! Towards model independent fault and error diagnosis
        Proc. of International Test Conference, Oct. 1998.
      • Jawahar Jain, William Adams, Masahiro Fujita
        An Efficient Sampling based scheme for computing variable ordering
        ICCAD, Nov. 1998.
      • R. Murgai, J. Jain, M. Fujita
        Efficient scheduling techniques for ROBDD construction
        VLSI Design, India, Jan., 1999.
      • Rajarshi Mukherjee, Jawahar Jain, Koichiro Takayama, Masahiro Fujita, Don Fussell, Jacob Abraham
        An Efficient Filter Based Approach for Combinational Verification
        DATE, Munich, March 1999.
      • S. Rajan, M. Fujita, Ashok Sudarsanam, and Sharad Malik
        Development of an Optimizing Compiler for Fujitsu Fixed Point DSP
        Proceedings of the International Workshop in Hardware/Software Codesign (CODES'99), May 1999, Rome, Italy.
      • V. Boppana, R. Mukherjee, J. Jain. M. Fujita
        Multiple Error Diagnosis Based on XLISTS
        DAC, June 1999.
      • A. Biere, A. Climatti. E.M. Clarke, M. Fujita, Y. Zhu
        Symbolic Model Checking using SAT procedures instead of BDDs
        DAC, June 1999.
      • S. Rajan, V. Boppana, K. Takayama, and M. Fujita
        Efficient Model Checking for Synchronizable Finite State Machines
        Proceedings of the International Conference on Computer-Aided Verification (CAV'99), July 1999.
    6. 招待講演
      • M. Fujita
        Logic Design Assistance with Temporal Logic
        invited talk at IEEE International Symposium on Multiple Valued Logic, Spain, May 1989.
      • M. Fujita
        Practical Techniques of Formal Verification
        IFIPWG10.2 Seminar on Formal Verification, India, Jan. 1996.
      • M. Fujita, R. Murgai
        Delay Estimation and Optimization of Logic Circuit: A Survey
        invited paper at ASPDAC97, Japan, Jan. 1997.
      • M. Fujita
        Binary Decision Diagrams and its extensions
        invited talk at International Workshop on Reed-Muller expansion circuits, Oxford, Sept. 1997. 
      • M. Fujita
        Model Checking: Its Basics and Reality
        invited paper at ASPDAC98, Japan, Jan. 1998.
      • M. Fujita, R. Murgai
        Delay Estimation and Optimization of Technology Independent Logic Circuit: A Survey
        invited paper at ASICON98, Beijing, China, Oct. 1998.
      • M. Fujita, S. Rajan, A. Hu
        Two real formal verification experiences: ATM switch chip and parallel cache protocol
        invited paper at Workshop on current trends in applied formal method, Boppard, Germany, 1998.
      • 藤田(モデレータ)
        パネルディスカッション:システムLSIに期待される設計手法革命 − システムLSI設計者がCADに望むこと
        情報処理学会システムLSI設計技術研究会, 1999年7月.
    7. 創造的活動
      • 特許
        US5535132 Variable sequence determining method for a dichotomy determination graph
        US5461574 Method of expressing a logic circuit
  2. 教育実績
    期間  担当講義名  勤務先  職務 
    1987年9月-12月  University of Illinois Urbana ChampaignよりPhDの学生を受け入れ、研究 指導。  富士通研究所  研究員 
    1992年4月-7月  Stanford大学京都校からPhDの学生を受け入れ、研究指導。  富士通研究所  研究員 
    1994年-1999年  University of California Berkeley, Carnegie Mellon University, Massachusetts Institute of Technology, University of Colorado Boulder, University of Texas Austinから、PhDの学生を夏期3ヶ月受け入れ、研究指導。  米国富士通研究所 ディレクタ 
    1997, 1999年   Carnegie Mellon University PhD審査委員  米国富士通研究所  ディレクタ 
    1998年   University of Colorado Boulder PhD審査委員  米国富士通研究所  ディレクタ 
  3. 社会的貢献
    1. 学協会役員等
      • なし
    2. 学会誌、国際的学術雑誌編集委員等
      • IEEE Transaction on CAD, Associate Editor (1992年 -1999年)
      • Kluwer Publisher Journal: Formal methods in system design, Editor (1993年-現在に至る)
    3. 国際会議、国際シンポジウム組織委員、プログラム委員等
      • Daghstul (German government) seminar on decision diagrams: 組織委員1997年
      • IEEE High Level Design Validation Workshop: 組織委員1997-1999年
      • IEEE/ACM International Workshop on Logic Syntehsis: 組織委員1995年, 1997年
      • IEEE/ACM International Conference on Computer Design: 組織委員1993年, 1994年
      • IEEE/ACM International Conference on Computer-Aided-Design(ICCAD):プログラム委員1991-1995年, 1998-1999年
      • IEEE/ACM International Conference on Computer Design (ICCD): プログラム委員1992-1998年
      • IEEE/ACM International Workshop on Logic Synthesis: プログラム委員1991年, 1993年, 1995年, 1997年, 1998年, 1999年
      • IFIP WG10.5 Computer Hardware Description Languages (CHDL): プログラム委員1993年, 1995年, 1997年
      • IFIP WG10.5 VLSI Conferences: プログラム委員1997年, 1999年
      • IEEE/ACM International Symposium on System Synthesis: プログラム委員1998年, 1999年
      • IFIP WG10.5 International Workshop on Reed-Muller circuits: プログラム委員1993年, 1995年, 1997年, 1999年
      • European Test and Design Conference (EDTC): プログラム委員1993-1995年
      • Tau Workshop on Timing Issues: プログラム委員1993年, 1995年
      • ACM International Symposium on FPGA: プログラム委員1996年
      • International Symposium on Low Power Electronics: プログラム委員1996年, 1997年
    4. 公的な審議会、委員会等における貢献
      • 1990年-現在、IFIP WG10.5委員
  4. その他
    1. 受賞歴
      • 1987年 情報処理学会学術奨励賞
      • 1991年 情報処理学会設計自動化研究会研究賞
      • 1991年 元岡賞
      • 1994年 情報処理学会坂井特別賞
      • IFIP WG10.5 VLSI conference 1997 Distinguished paper award
    2. 学内における管理運営などの活動
      • なし