7th International Symposium on Representations and Methodology of Future Computing Technologies RM2005 (formerly ReedMuller) September 5-6, 2005 Tokyo, Japan

Thanks to the new printing schedule of the proceedings and also due to many requests, the deadline of paper submissions have been FURTHER extended.
If you intend to submit your paper, please notify us immediately by e-mail.

Molecular scale computing, Nanotechnology, as well as Quantum computing are trends in future computing that might offer the way to circumvent the approaching bottom of Moore's law for traditional silicon based technologies. For synthesis and design new types of representations are required to exploit the full potential of these new technologies. In the past, e.g. AND-EXOR based representations have proven to be simpler than standard AND-OR representations for switching functions, while on the other hand showing many different properties. Decision diagrams have been extensively studied and have provided powerful new techniques for verification and synthesis.

The goal of the symposium is to bring together researchers in these and related fields to discuss new approaches and results. This year the symposium took place in Tokyo, Japan. Previous workshops have been held in Trier (Germany) in 2003, in Starkville, Mississippi (USA) in 2001, in Victoria, BC (Canada) in 1999, in Oxford(UK) in 1997, in Tokyo (Japan) in 1995, and in Hamburg(Germany) in 1993.

A non-restrictive list of interests includes the following topics:

• Representations for Molecular Scale Computing
• Representations for Quantum Computing
• Representations for Nanotechnology
• Graph-based representations of logic functions: Binary Decision Diagrams, Functional Decision Diagrams, e.a.
• XOR-based logic synthesis and verification
• Reed-Muller expressions, Kronecker expressions, Exclusive-Or/Sum-of-Products Expressions (ESOPs), Multi-level circuits
• New types of representations for discrete functions
• AND-OR vs. AND-XOR complexity
• Easily testable circuits using XORs
• Implementation in silicon (FPLDs, FPGAs, ...)
• Applications of the Reed-Muller expansion, both inside and outside circuit design

Authors are invited to submit draft papers not exceeding 6 pages. The deadline of paper submission is April 8th, 2005 April 17th 2005. Each submission should be accompanied by a statement that if the paper is accepted the author(s) will present it at the workshop. Notifications of acceptance will be sent by the end of May 2005. A workshop handout will be distributed to the workshop attendees, and it is planed to publish selected papers in a more widely distributed form. Camera-ready papers are due July 8th 2005.

Submissions should be sent to the RM2005 workshop chair (rm05@cad.t.u-tokyo.ac.jp) to be received on or before April 8th 2005. Submissions should be sent by email as attached postscript or pdf file. If necessary, mailed submissions (5 copies) will be accepted. Please do not submit papers by fax.

Contact:
Masahiro Fujita (General Chair)
E-mail: fujita@ee.t.u-tokyo.ac.jp

Updated: May 25, 2005.