Hiroaki Yoshida

Address:

Takeda Bldg., Room 406, Yayoi 2-11-16, Bunkyo-ku, Tokyo 113-0032, JAPAN

Phone number:

+81-3-5841-6764 (Office & Fax)

E-mail: hiroaki@cad.t.u-tokyo.ac.jp
URL: http://www.cad.t.u-tokyo.ac.jp/~hiroaki

Hiroaki Yoshida received the B.S., M.S. and Ph.D. degrees in electronic engineering from the University of Tokyo, Tokyo, Japan, in 2000, 2002 and 2007, respectively. From 2002 to 2006, he was a Senior Software Engineer at Zenasis Technologies, Inc., in San Jose, CA., where he was working on the development of a leading-edge logic/physical/transistor-level timing optimization tool.

He is currently a Project Assistant Professor with VLSI Design and Education Center, the University of Tokyo. His research interests include high-level, logic-level and transistor-level optimization of high-performance digital circuits.

• Program Committee, ESLsyn 2011
• EDA Symposium Technical Program Committee, ICCCAS 2010
• Steering Committee, IPSJ SIGSLDM (from April 2009)
• Program Committee, FIT 2009, FIT 2010, FIT 2011, FIT 2012
• Session Chair, SASIMI 2009
• Session Co-moderator, DATE 2008

Energy-Efficient Hardware for Post-Silicon ECO

• An Energy-Efficient Patchable Accelerator For Post-Silicon Engineering Changes.
  
  H. Yoshida and M. Fujita, in Proc. of CODES+ISSS,, Oct. 2011.
  (Best Paper Candidate)
• Increasing Yield Using Partially-Programmable Circuits.
  
  S. Yamashita, H. Yoshida and M. Fujita, in Proc. of SASIMI, Oct. 2010.
  (Best Paper Award)

Transistor-Level Optimization for High-Performance Digital Circuits

• Accurate Pre-layout Estimation of Standard Cell Characteristics.
  
  H. Yoshida, K. De and V. Boppana, in Proc. of DAC, Jun. 2004.
  • Used as an area estimation engine in a well-known memory performance estimation tool CACTI (HP Labs)
  • Used as a delay model in Network-on-Chip simulator Orion (Princeton University)
• Performance-Constrained Transistor Sizing for Different Cell Count Minimization.
  
  H. Yoshida and M. Fujita, IPSJ Journal of Information Processing, Dec. 2010.

Exact Minimum Synthesis of Logic Circuits

• Exact Minimum Factoring of Incompletely Specified Logic Functions via Quantified Boolean Satisfiability.
  
  H. Yoshida and M. Fujita, IPSJ Trans. on SLDM, Feb. 2011.
• A Structural Approach for Transistor Circuit Synthesis.
  
  H. Yoshida, M. Ikeda and K. Asada, IEICE Trans. on Fundamentals, Dec. 2006.

Complete Publication/Award List

Invited Talks

• Rule-based Equivalence Checking of System-level Design Descriptions.
  
  H. Yoshida and M. Fujita, in Proc. of ICCCAS, Jun. 2009.

Book Chapters

• Fundamentals of System LSI Design Automation, Baifukan Co., Ltd., 2005. (Chapter 3 and 4)

Patents

• Method, system and apparatus of IC design optimization via creation of design-specific cell from post-layout patterns.
  
  P. Majumder, B. Kumthekar, N. R. Shah, J. Mowchenko, P. A. Chavda, Y. Kojima, H. Yoshida, and V. Boppana, U.S. Patent No. 7,941,776, May 2011.
• Accelerator and data processing method.
  
  H. Yoshida and M. Fujita, U.S. Patent Application 61/446208.
• Accelerator and data processing method.
  
  H. Yoshida, M. Fujita, Japan Patent Application 2010-193136.
• Circuit verification device, circuit verification system and LSI with circuit verification function.
  
  H. Yoshida, M. Fujita, and S. Morishita, U.S. Patent Application 61/152349.
• Circuit verification device, circuit verification system and LSI with circuit verification function.
  
  H. Yoshida, M. Fujita, and S. Morishita, Japan Patent Application Publication 2009-294738.
• System and method for automated accurate pre-layout estimation of standard cell characteristics.
  
  H. Yoshida and V. Boppana, U.S. Patent Application 20050229142.