Hiroaki Yoshida received the B.S., M.S. and Ph.D. degrees in
electronic engineering
from
the University of Tokyo,
Tokyo, Japan, in 2000, 2002 and 2007, respectively. From 2002 to 2006, he
was a Senior Software Engineer at Zenasis Technologies, Inc., in San Jose,
CA., where he was working on the development of a leading-edge
logic/physical/transistor-level timing optimization tool.
He is currently a
Project Assistant Professor with
VLSI Design and Education Center,
the University of Tokyo.
His research interests include high-level, logic-level and transistor-level
optimization of high-performance digital circuits.