Hiroaki Yoshida


Japanese | English
Project Assistant Professor
VLSI Design and Education Center, University of Tokyo

Contact Information

Address:  Takeda Bldg., Room 406, Yayoi 2-11-16, Bunkyo-ku, Tokyo 113-0032, JAPAN
Phone number:  +81-3-5841-6764 (Office & Fax)
E-mail: hiroaki@cad.t.u-tokyo.ac.jp
URL: http://www.cad.t.u-tokyo.ac.jp/~hiroaki

Biography (Resume)

A picture of me
Hiroaki Yoshida received the B.S., M.S. and Ph.D. degrees in electronic engineering from the University of Tokyo, Tokyo, Japan, in 2000, 2002 and 2007, respectively. From 2002 to 2006, he was a Senior Software Engineer at Zenasis Technologies, Inc., in San Jose, CA., where he was working on the development of a leading-edge logic/physical/transistor-level timing optimization tool.

He is currently a Project Assistant Professor with VLSI Design and Education Center, the University of Tokyo. His research interests include high-level, logic-level and transistor-level optimization of high-performance digital circuits.

Professional Activities

Research Topics

Energy-Efficient Hardware for Post-Silicon ECO

Transistor-Level Optimization for High-Performance Digital Circuits

Exact Minimum Synthesis of Logic Circuits


Complete Publication/Award List

Invited Talks, Books and Patents

Invited Talks

Book Chapters

Patents

  • Method, system and apparatus of IC design optimization via creation of design-specific cell from post-layout patterns.
    P. Majumder, B. Kumthekar, N. R. Shah, J. Mowchenko, P. A. Chavda, Y. Kojima, H. Yoshida, and V. Boppana, U.S. Patent No. 7,941,776, May 2011.
  • Accelerator and data processing method.
    H. Yoshida and M. Fujita, U.S. Patent Application 61/446208.
  • Accelerator and data processing method.
    H. Yoshida, M. Fujita, Japan Patent Application 2010-193136.
  • Circuit verification device, circuit verification system and LSI with circuit verification function.
    H. Yoshida, M. Fujita, and S. Morishita, U.S. Patent Application 61/152349.
  • Circuit verification device, circuit verification system and LSI with circuit verification function.
    H. Yoshida, M. Fujita, and S. Morishita, Japan Patent Application Publication 2009-294738.
  • System and method for automated accurate pre-layout estimation of standard cell characteristics.
    H. Yoshida and V. Boppana, U.S. Patent Application 20050229142.