Hiroaki Yoshida

Contact Information

Address:  Takeda Bldg., Room 406, Yayoi 2-11-16, Bunkyo-ku, Tokyo 113-0032, JAPAN
Phone number:  +81-3-5841-6764 (Office & Fax)
E-mail: hiroaki@cad.t.u-tokyo.ac.jp
URL: http://www.cad.t.u-tokyo.ac.jp/~hiroaki

Research Interest

High-level synthesis, Logic synthesis, Transistor-level optimization, Physical design, Fundamental CAD algorithms

Education

Bachelor of Engineering in Electronic Engineering (Apr. 1999 - Mar. 2000)
University of Tokyo, Tokyo

Master of Engineering in Electronic Engineering (Apr. 2000 - Mar. 2002)
University of Tokyo, Tokyo
Thesis: Synthesis Algorithms for Array Logic (in Japanese)

Ph.D. in Electronic Engineering (Apr. 2004 - Mar. 2007) (returned from a 2-year absence)
University of Tokyo, Tokyo
Thesis: Optimal Generation of Design-Specific Cell Libraries

Professional Experience

Zenasis Technologies, Inc., Campbell, CA (Apr. 2002 - Jun. 2006)
Senior Software Engineer
Senior Software Engineer developing a leading edge logic/physical/transistor-level optimization tool
  • Enhanced gate-level optimizers, gate remapping and buffer insertion, to achieve better optimization quality. The enhancement includes the algorithm design of physically-aware buffer insertion.
  • Enhanced clustering optimizer to achieve better optimization quality. The clustering optimizer is a primary driver of hybrid optimization, which is the company's core technology. The enhancement includes the design and implementation of physically-aware clustering optimizer.
  • Designed and implemented transistor sizing engine. This completely replaced an initial version of transistor sizer, which had several issues on optimization quality and runtime.
  • Worked with in-house team in performance tuning of static timing analysis engine. This project was successfully completed with a huge reduction in runtime and memory usage.
  • Designed and implemented pre-layout cell characteristics estimator. The estimator is a key to making the company's solution more realistic. Without the estimator, the optimization result could be completely wrong. A technical paper on this work was presented at Design Automation Conference 2004 (See Publications).
  • Enhanced logic-to-transistor mapping engine by overhauling the existing algorithm.
  • Designed and implemented hierarchical cell characterizer. The hierarchical cell characterizer reduces the runtime dramatically by performing a mix of static and dynamic analysis, while the regular cell characterizer performs only dynamic analysis. This successfully replaced the original characterizer with a huge runtime reduction.
  • Tested and debugged entire modules of the software.
  • Developed a number of utilities for setting up and customizing the tool.
  • Made a number of presentations/demos at Design Automation Conference 2003 & 2004 (world largest trade show in EDA industry).
  • Successfully completed the evaluation of the tool both in-house and at several customer sites. As well, helped the installation of the tool and gave training sessions at the sites.

Fujitsu Laboratories of America, Sunnyvale, CA (Aug. 2000 - Oct. 2000)
Summer intern, Advanced CAD research group
Supervisor: Dr. Rajeev Murgai
Summer Intern developing Fujitsu's internal layout-driven logic synthesis system
  • Designed and implemented simple gate decomposition/collapsing optimization engine.
  • Designed and implemented routing estimator based on steiner tree.

Skills

Operating Systems: Mac OS X, Windows, Unix and Linux operating systems
Programming Language: C/C++, Java, IA32 Assembly, Ruby, Python, Perl, Tcl/Tk, shell scripting(sh/bash)
Software Development Tools: gcc, gdb, gprof, Rational Purify, PureCov, Quantify
Hardware Description Language: VerilogHDL, VHDL
VLSI Design: Designed digital/analog full-custom chips (one of the chips was fabricated)
EDA Tools:  Synopsys Design Compiler, PrimeTime, Apollo, HSPICE
Cadence Virtuoso, BuildGates, PKS
Mentor Calibre, XCalibre
Language: Japanese(native language), English(fluent)

Publications

Journal Papers

  1. Exact Minimum Factoring of Incompletely Specified Logic Functions via Quantified Boolean Satisfiability.
    Hiroaki Yoshida and Masahiro Fujita, IPSJ Transactions on System LSI Design Methodology, vol. 4, pp. 70-79, Feb. 2011.
  2. Performance-Constrained Transistor Sizing for Different Cell Count Minimization.
    Hiroaki Yoshida and Masahiro Fujita, IPSJ Journal of Information Processing, vol. 18, pp. 252-262, Dec. 2010.
  3. Interconnect-Aware Pipeline Synthesis for Array-Based Architectures.
    Shanghua Gao, Hiroaki Yoshida, Kenshu Seto, Satoshi Komatsu, and Masahiro Fujita, IEICE Transactions on Fundamentals, vol. E92-A, no. 6, pp. 1464-1475, Jun. 2009.
  4. A Structural Approach for Transistor Circuit Synthesis.
    Hiroaki Yoshida, Makoto Ikeda and Kunihiro Asada, IEICE Transactions on Fundamentals, vol. E89-A, no. 12, pp.3529-3537, Dec. 2006.
  5. A Performance Driven Module Generator for a Dual-Rail PLA with Embedded 2-Input Logic Cells.
    Ulkuhan Ekinciel, Hiroaki Yamaoka, Hiroaki Yoshida, Makoto Ikeda, and Kunihiro Asada, IEICE Transactions on Information and Systems, vol. E88-D, no. 6, pp. 1159-1167, Jun. 2005.
  6. A Logic-Cell-Embedded PLA (LCPLA): An Area-Efficient Dual-Rail Array Logic Architecture.
    Hiroaki Yamaoka, Hiroaki Yoshida, Makoto Ikeda and Kunihiro Asada, IEICE Transactions on Electronics, vol. E87-C, no.2, pp.238-245, Feb. 2004.

International Conference Papers

  1. An Energy-Efficient Patchable Accelerator For Post-Silicon Engineering Changes.
    Hiroaki Yoshida and Masahiro Fujita, IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS),, Oct. 2011.
    (Best Paper Candidate)
  2. A Highly Energy-Efficient Accelerator Enabling Post-Silicon Engineering Changes and Its Patch Compilation Method
    Hiroaki Yoshida and Masahiro Fujita, Work-In-Progress Session, ACM/IEEE Design Automation Conference (DAC), June 2011.
  3. A Scalable Heuristic for Incremental High-Level Synthesis and Its Application to Reliable Computing.
    Shohei Ono, Hiroaki Yoshida and Masahiro Fujita, IEEE International Workshop on Reliability Aware System Design and Test (RASDAT), pp. 54-59, Jan. 2011.
  4. Low Power Programmable Controllers for Reliable and Flexible Computing.
    Masahiro Fujita, Hiroaki Yoshida and Jae-Ho Lee, IEEE International Workshop on Reliability Aware System Design and Test (RASDAT), pp. 19-24, Jan. 2011.
  5. Post-silicon debugging with high level design descriptions and programmable controllers.
    Masahiro Fujita, Bijan Alizadeh, Hiroaki Yoshida and Takeshi Matsumoto, International Workshop on Microprocessor Test and Verification (MTV), Dec. 2010.
  6. Increasing Yield Using Partially-Programmable Circuits.
    Shigeru Yamashita, Hiroaki Yoshida and Masahiro Fujita, in Proceedings of Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI), pp. 237-242, Oct. 2010.
    (Best Paper Award)
  7. Demonstration of Hardware Accelerated Formal Verification.
    Hiroaki Yoshida, Satoshi Morishita and Masahiro Fujita, in Proceedings of IEEE International Conference on Field-Programmable Technology (ICFPT), pp. 380-383, Dec. 2009.
  8. An SoC Platform with On-Chip Web Interface for In-Field Monitoring.
    Tetsuya Iizuka, Daisuke Nakamura, Hiroaki Yoshida, Satoshi Komatsu, Masahiro Sasaki, Makoto Ikeda, and Kunihiro Asada, in Proceedings of IEEE International SoC Design Conference (ISOCC), pp. 208-211, Nov. 2009.
  9. Rule-based Equivalence Checking of System-level Design Descriptions.
    Hiroaki Yoshida and Masahiro Fujita, in Proceedings of International Conference on Communications, Circuits and Systems (ICCCAS), pp. 1139-1143, June 2009. (invited)
  10. Improving the Accuracy of Rule-based Equivalence Checking of System-level Design Descriptions by Identifying Potential Internal Equivalences.
    Hiroaki Yoshida and Masahiro Fujita, in Proceedings of IEEE International Symposium on Quality Electronic Design (ISQED), pp. 360-370, Mar. 2009.
  11. Equivalence Checking of Loops Before and After Pipelining by Applying Symbolic Simulation and Induction.
    Shanghua Gao, Takeshi Matsumoto, Hiroaki Yoshida, and Masahiro Fujita, in Proceedings of Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI), pp. 380-385, Mar. 2009.
  12. Hardware-Accelerated Formal Verification.
    Hiroaki Yoshida, Satoshi Morishita, and Masahiro Fujita, International Workshop on Logic and Synthesis (IWLS), pp.247-252, Jun. 2008.
  13. Hardware/Software Co-Design/Execution Approach to Silicon Debug and Diagnosis.
    Masahiro Fujita, Hiroaki Yoshida, and Satoshi Morishita, IEEE International Workshop on Silicon Debug and Diagnosis (SDD), Apr. 2008.
  14. Performance-Constrained Different Cell Count Minimization for Continuously-Sized Circuits.
    Hiroaki Yoshida and Masahiro Fujita, in Proceedings of IEEE Design, Automation and Test in Europe (DATE), pp. 1099-1102, Mar. 2008.
  15. Exact Minimum Logic Factoring via Quantified Boolean Satisfiability.
    Hiroaki Yoshida, Makoto Ikeda and Kunihiro Asada, in Proceedings of IEEE International Conference on Electronics, Circuits and Systems (ICECS), pp. 1065-1068, Dec. 2006.
  16. Intelligent-Pad: On-Chip Interactive Test Platform For SoC Design Education.
    Makoto Ikeda, Ruotong Zheng, Satoshi Komatsu, Masahiro Sasaki, Hiroaki Yoshida, Tetsuya Iizuka, Mohamed Abbas, Kunihiro Asada, European Workshop on Microelectronics Education (EWME), Jun. 2006.
  17. An Algebraic Approach for Transistor Circuit Synthesis.
    Hiroaki Yoshida, Makoto Ikeda and Kunihiro Asada, in Proceedings of IEEE International Conference on Electronics, Circuits and Systems (ICECS), pp. 1-4, Dec. 2005.
  18. Accurate Pre-layout Estimation of Standard Cell Characteristics.
    Hiroaki Yoshida, Kaushik De and Vamsi Boppana, in Proceedings of ACM/IEEE Design Automation Conference (DAC), pp. 208-211, Jun. 2004.
  19. Constraint driven dual-rail PLA module generator with embedded 2-input logic cells.
    Ulkuhan Ekinciel, Hiroaki Yamaoka, Hiroaki Yoshida, Makoto Ikeda, and Kunihiro Asada, in Proceedings of IEEE Mediterranean Electrotechnical Conference (MELECON), pp. 189-192, May 2004.
  20. Logic Synthesis for PLA with 2-input Logic Elements.
    Hiroaki Yoshida, Hiroaki Yamaoka, Makoto Ikeda and Kunihiro Asada, in Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS), pp. 373-376, May 2002.
  21. A Dual-Rail PLA with 2-Input Logic Cells.
    Hiroaki Yamaoka, Hiroaki Yoshida, Makoto Ikeda and Kunihiro Asada, in Proceedings of IEEE European Solid-State Circuits Conference (ESSCIRC), pp. 203-206, Sep. 2002.
  22. Simultaneous Circuit Transformation and Routing.
    Hiroaki Yoshida, Motohiro Sera, Masao Kubo and Masahiro Fujita, in Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASPDAC) and 15th International Conference on VLSI Design (VLSI Design), pp. 479-483, Jan. 2002.
  23. Logic Synthesis for AND-XOR-OR Sense-Amplifying PLA.
    Hiroaki Yoshida, Hiroaki Yamaoka, Makoto Ikeda and Kunihiro Asada, in Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASPDAC) and 15th International Conference on VLSI Design (VLSI Design), pp. 166-171, Jan. 2002.
  24. Integration of Logic Synthesis and Layout processes by Generating Multiple Choices of Circuit Transformation.
    Hiroaki Yoshida, Motohiro Sera, Masao Kubo and Masahiro Fujita, IEEE International Workshop on Logic and Synthesis (IWLS), Jun. 2001.
  25. Layout-driven Logic Optimization.
    Robert Carragher, Rajeev Murgai, Supratik Chakraborty, Mukul R. Prasad, Ankur Srivastava, Navin Vemuri, Hiroaki Yoshida, Toshiyuki Shibuya and Yuzi Kanazawa, in Designer's forum proceedings of IEEE Design, Automation and Test in Europe (DATE) , Mar. 2001.
  26. Logic Minimization Using Node Complementation.
    Kenshu Seto, Hiroaki Yoshida, Makoto Ikeda and Kunihiro Asada, IEEE International Workshop on Logic Synthesis (IWLS), Jun. 2000.

Domestic Conference Papers

  1. Difference Computation of Design Descriptions For Incremental High-Level Synthesis
    Hiroaki Yoshida and Masahiro Fujita, IPSJ SIG Technical Report, vol. 2011-SLDM-149, no. 21, Mar. 2011. (in Japanese)
  2. Rapid SoC Prototyping Based on Virtual Multi-Processor Model.
    Hiroaki Yoshida and Masahiro Fujita, IEICE Technical Report, vol. 110, no. 316, pp. 7-12, Nov. 2010. (in Japanese)
    (Design Gaia 2010 Best Poster Award)
  3. A Scalable Heuristic for Incremental High-Level Synthesis.
    Shohei Ono, Hiroaki Yoshida and Masahiro Fujita, IEICE Technical Report, vol. 110, no. 316, pp. 13-18, Nov. 2010. (in Japanese)
    (IPSJ SIGSLDM Best Student Paper Award)
  4. Evaluation of FPGA Implementation Techniques for High-Performance SoC Prototypes.
    Hideo Tanida, Hiroaki Yoshida and Masahiro Fujita, IEICE Technical Report, vol. 110, no. 316, pp. 79-84, Nov. 2010. (in Japanese)
  5. A Highly Energy-Efficient Accelerator Enabling Post-Silicon Engineering Changes With Dynamic Patch Loading Mechanism.
    Hiroaki Yoshida and Masahiro Fujita, IPSJ SIG Technical Report, vol. 2010-SLDM-146, no. 6, Oct. 2010. (in Japanese)
  6. High-Level Synthesis for Highly-Efficient Accelerators Enabling Post-Silicon Engineering Change.
    Hiroaki Yoshida and Masahiro Fujita, Proceedings of IPSJ DA Symposium 2010, Sep. 2010. (in Japanese)
    (IPSJ SIGSLDM Best Paper Award)
  7. High-Level Synthesis of Programmable Hardware Accelerators Considering Potential Varieties.
    Hiroaki Yoshida and Masahiro Fujita, IEICE Technical Report, vol. 109, no. 462, pp. 67-72, Mar. 2010. (in Japanese)
  8. Automatic Generation of Design-Specific Cell Libraries.
    Hiroaki Yoshida and Masahiro Fujita, IEICE Technical Report, vol. 109, no. 315, pp. 179-184, Dec. 2009. (in Japanese)
    (IPSJ SIGSLDM Best Paper Award)
  9. Increasing Yield Using Partially-Programmable Circuits.
    Shigeru Yamashita, Hiroaki Yoshida and Masahiro Fujita, IEICE Technical Report, vol. 109, no. 315, pp. 125-130, Dec. 2009.
  10. A Formal Verification Method for On-Chip Programmable Interconnect.
    Takaaki Tagawa, Hiroaki Yoshida, and Masahiro Fujita, IEICE Technical Report, vol. 108, no. 478, pp. 95-100, Mar. 2009. (in Japanese)
  11. Automatic generation of Network-on-Chip topology under link length and latency constraint.
    Hideo Tanida, Hiroaki Yoshida, Takeshi Matsumoto, and Masahiro Fujita, IEICE Technical Report, vol. 108, no. 478, pp. 129-134, Mar. 2009. (in Japanese)
  12. Implementation and Chip Size Evaluation of an Realtime Onchip Monitoring System for Reliability of LSI Operation.
    Daisuke Nakamura, Hiroaki Yoshida, Satoshi Komatsu, Masahiro Sasaki, Makoto Ikeda and Kunihiro Asada, in Proceedings of IEICE General Conference 2009, Electronics(2), p. 107, Mar. 2009. (in Japanese)
  13. Improving the Accuracy of Rule-based Equivalence Checking of High-level Desciptions by Identifying Potential Internal Equivalences.
    Hiroaki Yoshida and Masahiro Fujita, IEICE Technical Report, vol. 108, no. 298, pp. 109-114, Nov. 2008. (in Japanese)
  14. Generation of High Coverage Property Set Using Counterexamples.
    Takeshi Matsumoto, Yeonbok Lee, Hiroaki Yoshida, Hisashi Yomiya, and Masahiro Fujita, IEICE Technical Report, vol. 108, no. 298, pp. 115-120, Nov. 2008. (in Japanese)
  15. A Hardware Acceleration for Semi-Formal Model Checking.
    Satoshi Morishita, Hiroaki Yoshida, and Masahiro Fujita, IEICE Technical Report, vol. 107, no. 559, pp. 115-120, Mar. 2008. (in Japanese)
    (IPSJ Computer Science Field Incentive Award, IPSJ SIGSLDM Best Paper Award)
  16. Specification description and high-level design methodology of SoC considering design reuse.
    Yeonbok Lee, Yuji Ishikawa, Yoshihisa Kojima, Hiroaki Yoshida, Hisashi Yomiya, and Masahiro Fujita, IEICE Technical Report, vol. 107, no. 505, pp. 55-60, Mar. 2008.
  17. Synthesis of Read-Once Switch Network.
    Hiroaki Yoshida, Makoto Ikeda and Kunihiro Asada, in Proceedings of IEICE Society Conference 2006, A-3-9, p. 53, Sep. 2006. (in Japanese)
  18. Design of Program Environment for SoC On-chip Test.
    Taisuke Murata, Hiroaki Yoshida, Makoto Ikeda and Kunihiro Asada, in Proceedings of IEICE General Conference 2009, Electronics(2), p. 76, Mar. 2006. (in Japanese)
  19. Exact Minimum Logic Factoring via Quantified Boolean Satisfiability.
    Hiroaki Yoshida, Makoto Ikeda and Kunihiro Asada, IEICE Technical Report, vol. 105, no. 443, pp. 41-46, Dec. 2005. (in Japanese)
  20. An Algebraic Approach for Synthesizing Circuits with Minimum Number of Transistors.
    Hiroaki Yoshida, Makoto Ikeda and Kunihiro Asada, Proceedings of IPSJ DA Symposium 2005, pp. 133-138, Aug. 2005. (in Japanese)
  21. Accurate Pre-layout Estimation of Intra-cell Parasitics Using Fast Transistor-level Placement.
    Hiroaki Yoshida, Kaushik De, Vamsi Boppana, Makoto Ikeda and Kunihiro Asada, IEICE Technical Report, vol. 104, no. 478, pp. 7-12, Dec. 2004. (in Japanese)
  22. Hierarchical Layout Synthesis for CMOS Logic Cells via Boolean Satisfiability.
    Tetsuya Iizuka, Hiroaki Yoshida, Makoto Ikeda and Kunihiro Asada, IEICE Technical Report, vol. 104, no. 478, pp. 1-6, Dec. 2004. (in Japanese)
  23. Logic Synthesis for PLA with 2-input Logic Elements.
    Hiroaki Yoshida, Hiroaki Yamaoka, Makoto Ikeda and Kunihiro Asada, IEICE Technical Report, pp. 67-72, Nov. 2001. (in Japanese)
  24. Logic Synthesis for XOR-Based Dual-Rail PLA.
    Hiroaki Yoshida, Hiroaki Yamaoka, Makoto Ikeda and Kunihiro Asada, IPSJ DA Symposium, pp. 31-36, Jul. 2001. (in Japanese)

Patents

  1. Method, system and apparatus of IC design optimization via creation of design-specific cell from post-layout patterns.
    Purnabha Majumder, Balakrishna Kumthekar, Nimish R. Shah, John Mowchenko, Pramit A. Chavda, Yoshihisa Kojima, Hiroaki Yoshida, and Vamsi Boppana, U.S. Patent No. 7,941,776, May 2011.
  2. Accelerator and data processing method.
    Hiroaki Yoshida and Masahiro Fujita, U.S. Patent Application 61/446208.
  3. Accelerator and data processing method.
    Hiroaki Yoshida, Masahiro Fujita, Japan Patent Application 2010-193136.
  4. Circuit verification device, circuit verification system and LSI with circuit verification function.
    Hiroaki Yoshida, Masahiro Fujita, and Satoshi Morishita, U.S. Patent Application 61/152349.
  5. Circuit verification device, circuit verification system and LSI with circuit verification function.
    Hiroaki Yoshida, Masahiro Fujita, and Satoshi Morishita, Japan Patent Application Publication 2009-294738.
  6. System and method for automated accurate pre-layout estimation of standard cell characteristics.
    Hiroaki Yoshida and Vamsi Boppana, U.S. Patent Application 20050229142.

Awards

  1. An Energy-Efficient Patchable Accelerator For Post-Silicon Engineering Changes.
    Hiroaki Yoshida and Masahiro Fujita, IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), Best Paper Candidate, Oct. 2011.
  2. High-Level Synthesis for Highly-Efficient Accelerators Enabling Post-Silicon Engineering Change.
    Hiroaki Yoshida, and Masahiro Fujita, IPSJ SIGSLDM Best Paper Award, Aug. 2011.
  3. A Scalable Heuristic for Incremental High-Level Synthesis.
    Shohei Ono, Hiroaki Yoshida, and Masahiro Fujita, IPSJ SIGSLDM Best Student Paper Award, Aug. 2011.
  4. Rapid SoC Prototyping Based on Virtual Multi-Processor Model.
    Hiroaki Yoshida, and Masahiro Fujita, Design Gaia 2010 Best Poster Award, Nov. 2010.
  5. Increasing Yield Using Partially-Programmable Circuits.
    Shigeru Yamashita, Hiroaki Yoshida and Masahiro Fujita, Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI), Best Paper Award, Oct. 2010.
  6. Automatic Generation of Design-Specific Cell Libraries.
    Hiroaki Yoshida, and Masahiro Fujita, IPSJ SIGSLDM Best Paper Award, Sep. 2010.
  7. A Hardware Acceleration for Semi-Formal Model Checking.
    Satoshi Morishita, Hiroaki Yoshida, and Masahiro Fujita, IPSJ Computer Science Field Incentive Award, Mar. 2009.
  8. A Hardware Acceleration for Semi-Formal Model Checking.
    Satoshi Morishita, Hiroaki Yoshida, and Masahiro Fujita, IPSJ SIGSLDM Best Paper Award, Mar. 2009.
  9. A Module Generator for a Dual-Rail PLA with 2-input Logic Cells.
    Hiroaki Yamaoka, Hiroaki Yoshida, Ulkuhan Ekinciel and Kunihiro Asada, 5th Nikkei-BP LSI IP Design Award (IP Award), Jun. 2003.
  10. A Module Generator for a Dual-Rail PLA with 2-input Logic Cells.
    Hiroaki Yamaoka, Hiroaki Yoshida, Ulkuhan Ekinciel and Kunihiro Asada, 4th Nikkei-BP LSI IP Design Award (Challenge Award), May. 2002.

Other Presentations

  1. Integration of Logic Synthesis and Layout processes by Generating Multiple Choices of Circuit Transformation.
    Hiroaki Yoshida, Motohiro Sera, Masao Kubo, Satoshi Komatsu and Masahiro Fujita, ACM/SIGDA University Booth at ACM/IEEE Design Automation Conference (DAC), Jun. 2001.