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2018

研究論文 Journal Papers

Heming Sun ; Zhengxue Cheng ; Amir Masoud Gharehbaghi ; Shinji Kimura ; Masahiro Fujita: Approximate DCT Design for Video Encoding Based on Novel Truncation Scheme: IEEE Transactions on Circuits and Systems I: Regular Papers, Vol. 66 , pp. 1517 – 1530 (2019)
Binod Kumar ; Kanad Basu ; Masahiro Fujita ; Virendra Singh: Post-Silicon Gate-Level Error Localization with Effective & Combined Trace Signal Selection: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Y. KIMURA, A. M. GHAREHBAGHI, M. FUJITA: C Description Reconstruction Method from a Revised Netlist for ECO Support: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences, Vol.E101-A, No.4, pp.685-696

国際会議 International Conference Papers

Yukio Miyasaka, Ashish Mittal, Masahiro Fujita: Synthesis of Algorithm Considering Communication Structure of Distributed/Parallel Computing: International Symposium on Quality Electronic Design (ISQED) 2019, March 2019: Session 1A.4
Peikun Wang, Amir Masoud Gharehbaghi, Masahiro Fujita: Automatic Test Pattern Generation for Double Stuck-at Faults Based on Test Patterns of Single Faults: International Symposium on Quality Electronic Design (ISQED) 2019, March 2019: Session 4B.3
Ankit Jindal ; Binod Kumar ; Nitish Jindal ; Masahiro Fujita ; Virendra Singh: Silicon Debug with Maximally Expanded Internal Observability Using Nearest Neighbor Algorithm: 2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), July 2018: pp. 46-51
Darshit Vaghani ; Satyadev Ahlawat ; Jaynarayan Tudu ; Masahiro Fujita ; Virendra Singh: On Securing Scan Design Through Test Vector Encryption: 2018 IEEE International Symposium on Circuits and Systems (ISCAS): May 2018: DOI: 10.1109/ISCAS.2018.8351212

国内学会等 Domestic Conference Papers

王　培坤・アミルマサウドガラバギ・藤田昌宏, 「多重縮退故障用インクリメンタルテストパターン自動生手法.」電子情報通信学会技術研究報告信学技報 VLD2018-74 (2019).
Xiaoran Han・Amir Masoud Gharehbaghi・Masahiro Fujita, “Partial logic synthesis by using sum of products or product of sums based quantified boolean formulae,” システムとLSIの設計技術研究会（IPSJ-SLDM）2018年5月, VLD2018-1
合田瑛洋，藤田昌宏, 「テンプレートと状態遷移表現を用いたシステム最適化手法」システムとLSIの設計技術研究会（IPSJ-SLDM）2018年5月
宮坂幸雄，藤田昌宏, 「複数コア／FPGAチップ間の通信構造に配慮したアルゴリズムの自動合成」システムとLSIの設計技術研究会（IPSJ-SLDM）2018年5月

その他 Others

Binod Kumar, Tomohiro Maruoka, Amir Masoud Gharehbaghi, Masahiro Fujita: Honorable Mention ICCAD 2018 CAD Contest

2017

研究論文 Journal Papers

Masahiro Fujita: Automatic correction of logic bugs in hardware design: Partial logic synthesis. Procedia Computer Science 125: 790-800
Peikun Wang, Conrad Jinyong Moore, Amir Masoud Gharehbaghi, Masahiro Fujita: An ATPG Method for Double Stuck-At Faults by Analyzing Propagation Paths of Single Faults. IEEE Transactions on Circuits and Systems I. 65(3): 1063-1074
Toral Shah, Anzhela Matrosova, Masahiro Fujita, Virendra Singh: Multiple Stuck-at Fault Testability Analysis of ROBDD Based Combinational Circuit Design. Journal of Electronic Testing 34(1): 53-65
T. Komawaki, M. Yabuuchi, R. Kishida, J. Furuta, T. Matsumoto, K. Kobayashi: Replication of Random Telegraph Noise by Using a Physical-Based Verilog-AMS Model. IEICE Trans. Fundamentals, E100-A(12): 2758-2763
Tatsuya Onuki, Wataru Uesugi, Atsuo Isobe, Yoshinori Ando, Satoru Okamoto, Kiyoshi Kato, Tri Rung Yew, JY Wu, Chi Chang Shuai, Shao Hui Wu, James Myers, Klaus Doppler, Masahiro Fujita, Shunpei Yamazaki: Embedded memory and ARM cortex-M0 core using 60-nm C-axis aligned crystalline indium–gallium–zinc oxide FET integrated with 65-nm Si CMOS. IEEE Journal of Solid-State Circuits 52(4): 925-932

国際会議 International Conference Papers

Binod Kumar, Ankit Jindal, Masahiro Fujita, Virendra Singh: Combining restorability and error detection ability for effective trace signal selection. GLS-VLSI 2017: 191-196
Amir Masoud Gharehbaghi, Masahiro Fujita: A new approach for diagnosing bridging faults in logic designs. IEEE International Symposium on Circuits and Systems (ISCAS), May 2017:
Conrad J. Moore, Peikun Wang, Amir Masoud Gharehbaghi, Masahiro Fujita: Test pattern generation for multiple stuck-at faults not covered by test patterns for single faults. IEEE International Symposium on Circuits and Systems (ISCAS), May 2017:
Heming Sun, Zhengxue Cheng, Amir Masoud Gharehbaghi, Shinji Kimura, Masahiro Fujita: A low-cost approximate 32-point transform architecture. IEEE International Symposium on Circuits and Systems (ISCAS), May 2017:
Takahiko Ishizu, Shuhei Nagatsuka, Momoyo Yamaguchi, Atsuo Isobe, Yoshinori Ando, Daisuke Matsubayashi, Kiyoshi Kato, Hai Biao Yao, Chi Chang Shuai, Hung Chan Lin, J Y Wu, Masahiro Fujita, and Shunpei Yamazaki: A 140 MHz 1 Mbit 2T1C Gain-Cell Memory with 60-nm Indium-Gallium-Zinc Oxide Transistor Embedded into 65-nm CMOS Logic Process Technology. IEEE Symposium on VLSI Circuits, June 2017: 162-163
Binod Kumar, Kanad Basu, Ankit Jindal, Brajesh Pandey, Masahiro Fujita: A Formal Perspective on Effective Post-silicon Debug and Trace Signal Selection. VDAT 2017: 753-766
Nihar Hage, Rohini Gulve, Masahiro Fujita, Virendra Singh: Instruction-based self-test for delay faults maximizing operating temperature. IEEE International Symposium on On-Line Testing and Robust System Design (IOLTS), July 2017: 259-264
Binod Kumar, Kanad Basu, Masahiro Fujita, Virendra Singh: RTL level trace signal selection and coverage estimation during post-silicon validation. IEEE International High Level Design Validation and Test Workshop (HLDVT), Oct. 2017: 59-66
Masahiro Fujita: An approach to approximate computing: Logic transformations for one-minterm changes in specification. IEEE International High Level Design Validation and Test Workshop (HLDVT), Oct. 2017: 91-94
Binod Kumar, Kanad Basu, Ankit Jindal, Masahiro Fujita: Improving post-silicon error detection with topological selection of trace signals. IEEE International Conference on Very Large Scale Integration (VLSI-SoC), Oct. 2017
Masahiro Fujita, Yusuke Kimura, Qinhao Wang: Template based synthesis for high performance computing. IEEE International Conference on Very Large Scale Integration (VLSI-SoC), Oct. 2017
Amir Masoud Gharehbaghi, Masahiro Fujita: A new approach for constructing logic functions after ECO. IEEE International Conference on Very Large Scale Integration (VLSI-SoC), Oct. 2017
Kentaro Iwata, Amir Masoud Gharehbaghi, Mehdi B. Tahoori, Masahiro Fujita: Post Silicon Debugging of Electrical Bugs Using Trace Buffers. Asian Test Symposium (ATS) Nov. 2017: 184-189
Shuhei Maeda, Satoru Ohshita, Kazuma Furutani, Yuto Yakubo, Takahiko Ishizu, Tomoaki Atsumi, Yoshinori Ando, Daisuke Matsubayashi, Kiyoshi Kato, Takashi Okuda, Masahiro Fujita, Shunpei Yamazaki: A 20ns-write 45ns-read and 10 14-cycle endurance memory module composed of 60nm crystalline oxide semiconductor transistors. ISSCC 2018: 484-486

国内学会等 Domestic Conference Papers

大貫達也・磯部敦生・安藤善範・岡本　悟・加藤　清・T R Yew・Chen Bin Lin・J Y Wu・Chi Chang Shuai・Shao Hui Wu・James Myers・Klaus Doppler・藤田昌宏・山崎舜平, 信学技報 vol. 117, no. 9, ICD2017-17, pp. 89-93, 2017年4月
王　勤浩・木村悠介・ガラバギアミルマスード・藤田昌宏, 「RTL設計時のECOのためのテンプレートを用いたC記述合成手法」, 信学技報, vol. 117, no. 17, VLD2017-1, pp. 1-6, 2017年5月
岩田健太郎，ガラバギアミルマスード，藤田昌宏, 「トレースバッファを使用した電気的バグの発生箇所絞り込み手法」, システムとLSIの設計技術研究会（IPSJ-SLDM）2017年5月
丸岡大浩，藤田昌宏, 「隣接するブロック間のみに配線をもつFPGAに対する配置配線手法」, システムとLSIの設計技術研究会（IPSJ-SLDM）2017年5月
藤田昌宏 , ガラバギアミルマスード: ゲートの種類とゲート入力信号探索による論理最適化・デバッグ手法 (Logic Optimization and Debugging method Based on Input and Type Selection of a Gate). 電子情報通信学会技術研究報告信学技報 117(274): 151-156 (2017)
岡本朋大 , 川尾太郎 , 河野崇 , 藤田昌宏: 複数FPGAを用いたスパイキングニューラルネットワークシミュレーションの高速化 (Spiking Neural Network Simulation Accelerator Using Multiple FPGA Chips). 電子情報通信学会技術研究報告信学技報 117(274): 157-162 (2017)

その他 Others

Yusuke Kimura, Peikun Wang, Yukio Miyasaka, Kentaro Iwata, Xingming Le, Xiaoran Han, Amir Masoud Gharehbaghi, Masahiro Fujita: 3rd prize ICCAD 2017 CAD Contest

2016

研究論文 Journal Papers

Munehiro Kozuma, Yuki Okamoto, Takashi Nakagawa, Takeshi Aoki, Yoshiyuki Kurokawa, Takayuki Ikeda, Yoshinori Ieda, Naoto Yamade, Hidekazu Miyairi, Makoto Ikeda, Masahiro Fujita, Shunpei Yamazaki: Subthreshold Operation of CAAC-IGZO FPGA by Overdriving of Programmable Routing Switch and Programmable Power Switch. IEEE Trans. VLSI Syst. 25(1): 125-138 (2017)
Amir Masoud Gharehbaghi, Masahiro Fujita: Fast and Efficient Signature-Based Sub-Circuit Matching. IEICE Transactions 99-A(7): 1355-1365 (2016)

国際会議 International Conference Papers

Amir Masoud Gharehbaghi, Masahiro Fujita: A new approach for selecting inputs of logic functions during debug. ISQED 2017: 166-173
Sahand Salamat, Mehrnaz Ahmadi, Bijan Alizadeh, Masahiro Fujita: Systematic approximate logic optimization using don't care conditions. ISQED 2017: 419-425
Qinhao Wang, Yusuke Kimura, Masahiro Fujita: Methods of equivalence checking and ECO support under C-based design through reproduction of C descriptions from implementation designs. ISQED 2017: 432-437
T. Matsumoto, K. Kobayashi, H. Onodera: The Impact of RTN-Induced Temporal Performance Fluctuation Against Static Performance Variation, IEEE Electron Devices Technology and Manufacturing Conference (EDTM), Session 3B-2, 2017.
Binod Kumar, Ankit Jindal, Masahiro Fujita, Virendra Singh: Post-silicon observability enhancement with topology based trace signal selection. LATS 2017: 1-6
Toral Shah, Anzhela Matrosova, Binod Kumar, Masahiro Fujita, Virendra Singh: Testing multiple stuck-at faults of ROBDD based combinational circuit design. LATS 2017: 1-6
Binod Kumar, Ankit Jindal, Virendra Singh, Masahiro Fujita: A Methodology for Trace Signal Selection to Improve Error Detection in Post-Silicon Validation. VLSI Design 2017: 147-152
Nihar Hage, Rohini Gulve, Masahiro Fujita, Virendra Singh: On Testing of Superscalar Processors in Functional Mode for Delay Faults. VLSI Design 2017: 397-402
Taro Kawao, Masato Neishi, Tomohiro Okamoto, Amir Masoud Gharehbaghi, Takashi Kohno, Masahiro Fujita: Spiking Neural Network Simulation on FPGAs with Automatic and Intensive Pipelining. NOLTA 2016
Amir Masoud Gharehbaghi, Masahiro Fujita: A New Approach for Debugging Logic Circuits without Explicitly Debugging Their Functionality. ATS 2016: 31-36
Masahiro Fujita: Synthesizing and Completely Testing Hardware Based on Templates Through Small Numbers of Test Patterns. ATVA 2016: 3-10
Yusuke Kimura, Masahiro Fujita: Specification by existing design plus use-cases. HLDVT 2016: 40-45
Qinhao Wang, Yusuke Kimura, Masahiro Fujita: Automatically adjusting system level designs after RTL/gate-level ECO. HLDVT 2016: 108-112
Conrad J. Moore, A.M. Gharehbaghi, Masahiro Fujita: Automatic Test Pattern Generation for Multiple Stuck-At Faults: When Testing for Single Faults is Insufficient. ITC-CSCC 2016: 159-162
Yi Lu, Qinhao Wang, Amir Masoud Gharehbaghi, Masahiro Fujita: Communication Aware Compiler for Mesh-Structured Reconfigurable Processors on Single/Multi Chip. ITC-CSCC 2016: 605-608
Tatsuya Onuki, Wataru Uesugi, Hikaru Tamura, Atsuo Isobe, Yoshinori Ando, Satoru Okamoto, Kiyoshi Kato, T R Yew, Chen Bin Lin, J Y Wu, Chi Chang Shuai, Shao Hui Wu, James Myers, Klaus Doppler, Masahiro Fujita, Shunpei Yamazaki: Embedded memory and ARM Cortex-M0 core using 60-nm C-axis aligned crystalline indium-gallium-zinc oxide FET integrated with 65-nm Si CMOS. VLSI-Circuits 2016: 1-2

国内学会等 Domestic Conference Papers

木村悠介、石山薫太郎、藤田　昌宏, 「有界モデル検査ツールを用いたC言語プログラム部分合成」情報処理学会 DAシンポジウム2016, セッション3B-2, 2016-09-14
ムーアコンラッドジンヨン、ガラバギアミルマスード、藤田昌宏, 「単一故障用テストパターンでは不十分な場合を考慮した多重縮退故障用テストパターン自動生成手法」, 電子情報通信学会, VLSI設計技術研究会, 信学技報 116(96), 13-18, 2016

著書 Book

Shunpei Yamazaki and Masahiro Fujita (Ed.), “Physics and Technology of Crystalline Oxide Semiconductor CAAC-IGZO. Application to LSI,” WILEY, ISBN 9781119247340 (cloth) (2017)

2015

研究論文 Journal Papers

Takeshi Aoki, Yuki Okamoto, Takashi Nakagawa, Munehiro Kozuma, Yoshiyuki Kurokawa, Takayuki Ikeda, Naoto Yamade, Yutaka Okazaki, Hidekazu Miyairi, Masahiro Fujita, Jun Koyama, Shunpei Yamazaki: Normally-Off Computing for Crystalline Oxide Semiconductor-Based Multicontext FPGA Capable of Fine-Grained Power Gating on Programmable Logic Element With Nonvolatile Shadow Register. J. Solid-State Circuits 50(9): 2199-2211 (2015)
Masahiro Fujita: Toward Unification of Synthesis and Verification in Topologically Constrained Logic Design. Proceedings of the IEEE 103(11): 2052-2060 (2015)
Samaneh Ghandali, Bijan Alizadeh, Masahiro Fujita, Zainalabedin Navabi: Automatic High-Level Data-Flow Synthesis and Optimization of Polynomial Datapaths Using Functional Decomposition. IEEE Trans. Computers 64(6): 1579-1593 (2015)
Yuki Okamoto, Takashi Nakagawa, Takeshi Aoki, Masataka Ikeda, Munehiro Kozuma, Takeshi Osada, Yoshiyuki Kurokawa, Takayuki Ikeda, Naoto Yamade, Yutaka Okazaki, Hidekazu Miyairi, Masahiro Fujita, Jun Koyama, Shunpei Yamazaki: A Boosting Pass Gate With Improved Switching Characteristics and No Overdriving for Programmable Routing Switch Based on Crystalline In-Ga-Zn-O Technology. IEEE Trans. VLSI Syst. 23(3): 422-434 (2015)

国際会議 International Conference Papers

Payman Behnam, Bijan Alizadeh, Sajjad Taheri, Masahiro Fujita: Formally analyzing fault tolerance in datapath designs using equivalence checking. ASP-DAC 2016: 133-138
Masahiro Fujita: Detection of test Patterns with Unreachable States through Efficient Inductive-Invariant Identification. ATS 2015: 31-36
Ying Zhang, Zebo Peng, Jianhui Jiang, Huawei Li, Masahiro Fujita: Temperature-aware software-based self-testing for delay faults. DATE 2015: 423-428
Masahiro Fujita: Automatic identification of assertions and invariants with small numbers of test vectors. ICCD 2015: 463-466
Masahiro Fujita, Naoki Taguchi, Kentaro Iwata, Alan Mishchenko: Incremental ATPG methods for multiple faults under multiple fault models. ISQED 2015: 177-180
Sriram Karunagaran, Karuna P. Sahoo, Masahiro Fujita: Hardware in loop testing of an insulin pump. ITC 2015: 1-8
Masahiro Fujita: Logic analysis and optimization with quick identification of invariants through one time frame analysis. MEMOCODE 2015: 102-107
Masahiro Fujita: Analysis and testing on delays with two time frames. VLSI-SoC 2015: 13-18
Shridhar Choudhary, Amir Masoud Gharehbaghi, Takeshi Matsumoto, Masahiro Fujita: Trace signal selection methods for post silicon debugging. VLSI-SoC 2015: 258-263
Amir Masoud Gharehbaghi, Masahiro Fujita: Efficient signature-based sub-circuit matching. VLSI-SoC 2015: 280-285
Reza Sharafinejad, Bijan Alizadeh, Masahiro Fujita: UPF-based formal verification of low power techniques in modern processors. VTS 2015: 1-6

国内学会等 Domestic Conference Papers

RAD HOSSEIN IZADI, GHAREHBAGHI AMIR MASOUD, FUJITA MASAHIRO: Efficient Graph Matching Method for LUT-Networks, 電子情報通信学会, 信学技報 115(400), 43-48, 2016-01-19
川尾太郎, 河野崇, 藤田昌宏, 「高位合成による自動パイプライン化を利用したスパイキングニューラルネットワークシミュレーション高速化回路のFPGA実装」, 電子情報通信学会, 信学技報 115(339), 13-18, 2015-12-01
木村悠介, ガラバギアミルマスード, 藤田昌宏, 「実時間組み込みソフトウェア解析のためのHW/SW協調検査」, 電子情報通信学会, 信学技報 115(21), 39-44, 2015-05-14
Shridhar Chaudhary, Amir Masoud Gharehbaghi, Takeshi Matsumoto, Masahiro Fujita: Trace Signal Selection Methods for Post Silicon Debugging, 情報処理学会, 2015-SLDM-171(4), 1-6, 2015-05-07

2014

研究論文 Journal Papers

Yuki Okamoto, Takashi Nakagawa, Takeshi Aoki, Masataka Ikeda, Munehiro Kozuma, Takeshi Osada, Yoshiyuki Kurokawa, Takayuki Ikeda, Naoto Yamade, Yutaka Okazaki, Hidekazu Miyairi, Masahiro Fujita, Jun Koyama, Shunpei Yamazaki: A Boosting Pass Gate With Improved Switching Characteristics and No Overdriving for Programmable Routing Switch Based on Crystalline In-Ga-Zn-O Technology. IEEE Trans. VLSI Syst. 23(3): 422-434 (2015)
Amir Masoud Gharehbaghi, Masahiro Fujita: Automatic Rectification of Processor Design Bugs Using a Scalable and General Correction Model. IEICE Transactions 97-D(4): 852-863 (2014)
Satoshi Jo, Takeshi Matsumoto, Masahiro Fujita: SAT-based Automatic Rectification and Debugging of Combinational Circuits with LUT Insertions. IPSJ T. on System LSI Design Methodology7: 46-55 (2014)
Hikaru Tamura, Kiyoshi Kato, Takahiko Ishizu, Wataru Uesugi, Atsuo Isobe, Naoaki Tsutsui, Yasutaka Suzuki, Yutaka Okazaki, Yukio Maehashi, Jun Koyama, Yoshitaka Yamamoto, Shunpei Yamazaki, Masahiro Fujita, James Myers, Pekka Korpinen: Embedded SRAM and Cortex-M0 Core Using a 60-nm Crystalline Oxide Semiconductor. IEEE Micro 34(6): 42-53 (2014)

国際会議 International Conference Papers

Masahiro Fujita: On Implementation of LUT with Large Numbers of Inputs (Abstract Only). FPGA 2015: 277
Takanori Matsuzaki, Tatsuya Onuki, Shuhei Nagatsuka, Hiroki Inoue, Takahiko Ishizu, Yoshinori Ieda, Naoto Yamade, Hidekazu Miyairi, Masayuki Sakakura, Tomoaki Atsumi, Yutaka Shionoiri, Kiyoshi Kato, Takashi Okuda, Yoshitaka Yamamoto, Masahiro Fujita, Jun Koyama, Shunpei Yamazaki: 16.9 A 128kb 4b/cell nonvolatile memory with crystalline In-Ga-Zn oxide FET using Vt, cancel write method. ISSCC 2015: 1-3
Somayeh Sadeghi Kohan, Payman Behnam, Bijan Alizadeh, Masahiro Fujita, Zainalabedin Navabi: Improving polynomial datapath debugging with HEDs. ETS 2014: 1-6
Ying Zhang, Zebo Peng, Jianhui Jiang, Huawei Li, Masahiro Fujita: Temperature-aware software-based self-testing for delay faults. DATE 2015: 423-428
Masahiro Fujita, Naoki Taguchi, Kentaro Iwata, Alan Mishchenko: Incremental ATPG methods for multiple faults under multiple fault models. ISQED 2015: 177-180
Masahiro Fujita: Highly-Pipelined and Energy-Saved Computing with Arrays of Non-Volatile Memories. 2014 International Conference on Interdisciplinary Advances in Applied Computing, Amritapuri, India, Oct, 2014
Masahiro Fujita: Variation-Aware Analysis and Test Pattern Generation Based on Functional Faults. ISVLSI 2014: 273-277
Masahiro Fujita, Alan Mishchenko: Efficient SAT-based ATPG techniques for all multiple stuck-at faults. ITC 2014: 1-10
Sriram Karunagaran, Karuna P. Sahoo, Jayaraj Poroor, Masahiro Fujita: MAESTRO: A time-driven embedded testbed Architecture with Event-driven Synchronization. RTAS 2014: 237-248
Masahiro Fujita, Alan Mishchenko: Logic synthesis and verification on fixed topology. VLSI-SoC 2014: 1-6

2013

研究論文 Journal Papers

A.M. Gharehbaghi and M. Fujita, “Transaction Ordering in Network-on-Chips for Post-Silicon Validation,” IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E95-A, No. 12, pp. 2309-2318, Dec. 2012.
H. Tanida, M. R. Prasad, S. P. Rajan, and M. Fujita, “Automated System Testing of Dynamic Web Applications,” Communications in Computer and Information Science, Vol. 303, pp. 181-196, 2013.

国際会議 International Conference Papers

M. Fujita, “System-on-Chip (SoC) design techniques,” Tutorial in Third International Conference on Computing Communication and Networking Technologies 2012, Coimbatore, India, July 2012.
M. Fujita, “Development of High Performance and Flexible Computing Systems with Electronic Design Automation Algorithms,” International Conference on Signal Processing, Communications and Computing 2012, Hong Kong, Aug. 2012.
A.M. Gharehbaghi and M. Fujita, “Automatic Rectification of Design Errors in Complex Processors with Programmable Hardware,” Proc. of IEEE International Conference on Field Programmable Technology 2012, pp.141-146, Aug. 2012.
M. Fujita, “Simulation based analysis of cyberphysical systems,” Proc. of 15th Euromicro Conference on Digital System Design (DSD), pp. 485-492, Sep. 2012.
S. Ono, T. Matsumoto, and M. Fujita, “Automatic Assertion Extraction in Gate-Level Simulation Using GPGPUs,” Proc. of IEEE 30th International Conference on Computer Design, pp.522-523, Oct. 2012.
M. Bonato, G. Di Guglielmo, M. Fujita, F. Fummi, and G. Pravadelli, “Dynamic Property Mining for Embedded Software,” Proc. of the eighth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, pp.187-196, Oct. 2012.
T. Matsumoto, S. Ono, and M. Fujita, “An Efficient Method to Localize and Correct Bugs in High-Level Designs Using Counterexamples and Potential Dependence,” Proc. of IEEE/IFIP 20th International Symposium on Very Large Scale Integration, pp.291-294, Oct. 2012.
B. Alizadeh and M. Fujita, “A functional test generation technique for RTL datapaths,” Proc. of 17th IEEE International High Level Design Validation and Test Workshop, pp. 64-70, Nov. 2012.
M. Fujita, “Post-silicon verification and debugging with control FSM traces and patchable HW,” Proc. of 17th IEEE International High Level Design Validation and Test Workshop, pp. 100-107, Nov. 2012.
A.M. Gharehbaghi and M. Fujita, “Error Model Free Automatic Design Error Correction of Complex Processors Using Formal Methods,” Proc. of IEEE 21st Asia Test Symposium, pp.143-148, Nov. 2012.
S. Jo, T. Matsumoto, and M. Fujita, “SAT-based automatic rectification and debugging of combinational circuits with LUT insertions,” Proc. of IEEE 21st Asia Test Symposium, pp.19-24, Nov. 2012.
P. Mishra, M. Fujita, V. Singh, N. Tamarapalli, S. Kumar, and R. Mittal, “Post-Silicon Validation, Debug and Diagnosis,” Tutorial in 2013 26th International Conference on VLSI Design, Pune, India, Jan. 2013.
15. M. Fujita, “Microprocessor verification/debugging in abstracted level and their application to post-silicon debugging,” 4th IEEE International Workshop on Reliability Aware System Design and Test, Pune, India, Jan. 2013.
S. Jo, A.M. Gharehbaghi, T. Matsumoto, and M. Fujita, “Rectification of Advanced Microprocessors without Changing Routing on FPGAs,” Proc. of 21st ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, pp. 279-279, Feb. 2013.
M. Fujita, “Towards the Unification of Synthesis and Verification in Logic and Architectural Design,” Tutorial in Design, Automation & Test in Europe (DATE 13), March 2013.
M. Fujita, “ABV for SoC,” Tutorial in Design, Automation & Test in Europe (DATE 13), March 2013.

国内学会、研究会等 Domestic Conference Papers

小野翔平, 松本剛史, 藤田昌宏, “潜在的な依存関係を利用した高位設計デバッグ支援手法,” 電子情報通信学会技術研究報告, Vol. 112, No. 71, VLD2012-4, pp. 19-24, 2012年5月
大島浩資, 小野翔平, 松本剛史, 藤田昌宏, “誤差を有するシステムのシミュレーション結果に対する統計的解析とそのハードウェアによる高速化,” 電子情報通信学会技術研究報告, Vol. 112, No. 71, VLD2012-10, pp. 55-60, 2012年5月.
小野翔平, 松本剛史, 藤田昌宏 “ゲート回路シミュレーションにおけるGPGPU を利用したアサーション自動抽出,” 第25回回路とシステムワークショップ, pp. 426-431, 2012年7月.
谷田英生, 福井啓, 吉田浩章, 藤田昌宏, “FPGAとGPGPUを利用した津波伝搬シミュレーションの高速化・高効率化,” 情報処理学会研究報告, Vol. 2012-ARC-200, No. 3, pp. 1-8, 2012年4月.
谷田英生, Amir Masoud Gharehbaghi, 藤田昌宏, “形式的手法を用いたプロセッサ設計不具合の自動診断と修正,” 情報処理学会研究報告, Vol. 2012-ARC-202, No. 21, pp. 1-8, 2012年12月.

紀要、その他 Invited Talks & Tutorials

藤田昌宏, “高位合成、低消費電力用デザインの最適化、及び、等価検証における最近の傾向と今後の方向,” 基調講演, Calypto Tech Forum東京, 2012年4月.
M. Fujita, “Error Tolerance and Engineering Change with Partially Programmable Circuits and their SAT-Based Programming,” In Dagstuhl seminar (Seminar 12341): Verifying Reliability, Dagstuhl, Germany, Aug. 2012.
M. Fujita, “Formal Analysis and Verification of Multiple Programs Based on Difference Identification,” Verified Software Workshop and Summer School 2012, Shanghai, China, Aug. 2012.

2012

研究論文 Journal Papers

Y.Lee , T.Matsumoto ,and M.Fujita, “An Automatic Method of Mapping I/O Sequences of Chip Execution onto High-level Design for Post-Silicon Debugging“, IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E94-A, No. 7, pp.1519-1529, July 2011
R.Krishnamoor thy, S. Das, K. Varadarajan, M. Alle, M. Fujita, S K Nandy, and R. Narayan,“Data Flow Graph Par titioning Algorithms and Their Evaluations for Optimal Spatio-temporal Computation on a Coarse Grain Reconfigurable Architecture“, IPSJ Transations on System LSI Design Metholodogy, Vol. 4, pp. 193-209, Aug.2011

国際会議 International Conference Papers

M.Fujita, “Programmability based approach to post-silicon debug and recrification“, IEEE 29th VLSI Test Symposium, May 2011
M.Fujita, “Patchable Hardware Design“, 3rd IEEE Design for Reliability and Variability Workshop, May 2011
M.Fujita, “Formal Verification of Timing Error Recovery Algorithms for Pipelined Processors“, IEEE International Workshop on Processor Virification, Test and Debug(IWPVTD'11), May 2011
H.Yoshida and M.Fujita, “A Highly Energy-Efficient Accelerator Enabling Post-Silicon Engineering Changes and Its Patch Compilation Method“, Work-In-Progress Session, ACM/IEEE Desing Automation Conference(DAC), June 2011
G.Di Guglielmo, M.Fujita, F.Fummi, G.Pravadilli, “Model-Based Concolic Testing for Embedded Software“, Work-In-Progress Session, ACM/IEEE Design Automation Conference(DAC), June 2011
H.Tanida, M.Fujita, M.Prasad and S.P.Rajan, “Client-Tier Validation of Dynamic Web Applications“, Proc. of 6th International Conference on Software and Data Technologies, pp.86-95, July2011
G.Di Guglielmo, M.Fujita, F.Fummi, G.Pravadelli, and S.Soffia, “EFSM-based model-driven approach to concolic testing of system-level design“, Proc. of 9th IEEE/ACM International Conference on Formal Methods and Models for Codesign, pp.201-209, July 2011
H.Yoshida and M.Fujita, “An Energy-Efficient Patchable Accelerator For Post-Silicon Engineering Changes“, Proc. of IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, PP. 13-20, Oct.2011
M.Fujita, “Synthesizing, Verifying and Debugging SoC with FSM-Based Specification of On-Chip Communication Protocols“, Proc. of 9th International Symposium on Automated Technology for Verification and Analysis, pp.43-50, Oct.2011
M.Fujita, “High Level Verification and its Use at Post-SIlicon Debugging and Patching“, Proc. of 20th Asian Test Symposium, pp.464-469, Nov.2011
M.Fujita, “Structural and functional test generation from RTL/behavioral descriptions“, IEEE 12th Workshop on RTL and High Level Testing 2011, Nov,2011
B.Alizadeh and M.Fujita, “Modular equivalence verification of poluynominal datapaths with multiple word-length operands“, Proc. of 16th IEEE International High Level Design Validation and Test Workshop, pp.9-16, Nov.2011
A.M. Gharehbaghi and M.Fujita, “Formal Verification Guided Automatic Design Error Diagnosis and Correction of Complex Processors“, Proc. of 16th IEEE High Level Design Validation and Test Workshop, pp.121-127, Nov.2011
A.M. Gharehbaghi and M.Fujita, “Post-Silicon Debugging of Many-Core Systems by Identifiying Execution Pahts Through Constraint Refinement“, International Workshop on Constarints in Formal Verification, Nov.2011
M.Fujita “Accelerating Tsunami simulation with FPGA and GPU through automatic compilaion“, International Conference on Wireless Technologies for Humanitarian Relief, Dec.2011
R. Krishnamoorthy, M.Fujita, K.Varadarajan, and S.K. Nandy, “Interconnect-topology independent mapping algorithm for a Coarse Grained Reconfigurable Architecture“, Proc. of International Conference on Field-Programmable Technology 2011, pp.1-5, Dec.2011
M.Fujita and H.Yoshidam “Post-Silicon Patching for Verification/Debugging with High-Level Models and Programmable Logic“, Proc. of 17th Asia and South Pacific Design Automation Conference, pp.232-237, Jan.2012
Y.Yang, A.Veneris, N.Nicolici, and M.Fujita, “Automated Data Analysis Techniques for a Modern Silicon Debug Environment“, Proc. of 17th Asia and South Pacific Design Automation Conference, pp.298-303, Jan.2012
H.Mangassarian, H.Yoshida, A. Veneris, S.Yamashita, and M.Fujita, “On Error Tolerance and Engineering Change with Partially Programmable Circuits“, Proc. of 17th Asia and South Pacific Design Automation Conference, pp.695-700, Jan.2012
M.Fujita and H.Yoshida, “Post-silicon Debugging Targetting Electrical Errors with Patchable Controllers“, ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Feb.2012
A.M. Gharehbaghi and M.Fujita, “Transaction-Based Post-Silicon Debug of Many-Core System-on-Chips“, Proc. of International Symposium on Quality Electronic Design, pp.703-709, Mar.2012

国内会議 Domestic Conference Papers

福井啓,藤田昌宏, “FPGAを用いたSmith-Waterman Algorithmの高速化”電子情報通信学会技術研究報告, Vol.111, No.31, pp.67-72,2011年5月
福井啓,藤田昌宏, “高位合成ツールを利用したハードウエアアルゴリズムの最適化“, 情報処理学会研究報告, Vol.2011-SLDM-150, No.10, pp.1-6, 2011年5月
清水修一,松本剛史,藤田昌宏, “形式的検証を用いたプロセッサエラー回復機構の耐性評価手法の検討“, 情報処理学会研究報告, Vol.2011-SLDM-150, No.11, pp.1-6, 2011年5月
原田裕碁,松本剛史,藤田昌宏, “反例と設計分割に基づく高位設計に対する効率的な設計修正支援手法“, 情報処理学会研究報告, Vol.2011-SLDM-150, No.12, pp.1-6, 2011年5月
李在城,松本剛史,藤田昌宏, “論理関数の充足不可能性に注目した論理回路デバッグ手法の検討“, 情報処理学会研究報告, Vol.2011-SLDM-150, No.5, pp.1-6, 2012年3月
吉田浩章,藤田昌宏,“動作レベル・レジスタ転送レベル混在設計記述向け高位合成手法,”電子情報通信学会技術研究報告, Vol.111, No.450, pp.49-54, 2012年3月

紀要・その他 Others

西原祐, “Formal Verification of High-Level Design Based on Control/Data Separation“, 情報処理学会誌情報処理, 研究会推薦博士論文速報, Vol.52, No.10, p.1303, 2011年10月
李蓮福, “エラートレース解析に基づくVLSI設計のデバッグ支援“, 情報処理学会誌情報処理, 研究会推薦博士論文速報, Vol.53, No.3, p.275, 2012年3月

2011

論文誌 Journal Papers

Y. Lee, T. Matsumoto, and M. Fujita, “An Automatic Method of Mapping I/O Sequences of Chip Execution onto High-level Design for Post-Silicon Debugging,” IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E94-A, No. 7, pp. 1519-1529, July 2011.
R. Krishnamoorthy, S. Das, K. Varadarajan, M. Alle, M. Fujita, S K Nandy, and R. Narayan, “Data Flow Graph Partitioning Algorithms and Their Evaluations for Optimal Spatio-temporal Computation on a Coarse Grain Reconfigurable Architecture,” IPSJ Transations on System LSI Design Metholodogy, Vol. 4, pp. 193-209, Aug. 2011.

国際会議 International Conference Papers

M. Fujita, “Programmability based approach to post-silicon debug and rectification,” IEEE 29th VLSI Test Symposium, May 2011.
M. Fujita, “Patchable Hardware Design,” 3rd IEEE Design for Reliability and Variability Workshop, May 2011.
M. Fujita, “Formal Verification of Timing Error Recovery Algorithms for Pipelined Processors,” IEEE International Workshop on Processor Verification, Test and Debug (IWPVTD'11), May 2011.
H. Yoshida and M. Fujita, “A Highly Energy-Efficient Accelerator Enabling Post-Silicon Engineering Changes and Its Patch Compilation Method,” Work-In-Progress Session, ACM/IEEE Design Automation Conference (DAC), June 2011.
G. Di Guglielmo, M. Fujita, F. Fummi, G. Pravadelli, “Model-Based Concolic Testing for Embedded Software,” Work-In-Progress Session, ACM/IEEE Design Automation Conference (DAC), June 2011.
H. Tanida, M. Fujita, M. Prasad, and S. P. Rajan, “Client-Tier Validation of Dynamic Web Applications,” Proc. of 6th International Conference on Software and Data Technologies, pp. 86-95, July 2011.
G. Di Guglielmo, M. Fujita, F. Fummi, G. Pravadelli, and S. Soffia, “EFSM-based model-driven approach to concolic testing of system-level design,” Proc. of 9th IEEE/ACM International Conference on Formal Methods and Models for Codesign, pp.201-209, July 2011.
H. Yoshida and M. Fujita, “An Energy-Efficient Patchable Accelerator For Post-Silicon Engineering Changes,” Proc. of IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, pp. 13- 20, Oct. 2011.
M. Fujita, “Synthesizing, Verifying, and Debugging SoC with FSM-Based Specification of On-Chip Communication Protocols,” Proc. of 9th International Symposium on Automated Technology for Verification and Analysis, pp. 43-50, Oct. 2011.
M. Fujita, “High Level Verification and its Use at Post-Silicon Debugging and Patching,” Proc. of 20th Asian Test Symposium, pp. 464-469, Nov. 2011.
M. Fujita, “Structural and functional test generation from RTL/behavioral descriptions,” IEEE Twelfth Workshop on RTL and High Level Testing 2011, Nov. 2011.
B. Alizadeh and M. Fujtia, “Modular equivalence verification of polynomial datapaths with multiple word-length operands,” Proc. of 16th IEEE International High Level Design Validation and Test Workshop, pp. 9-16, Nov. 2011.
A. M. Gharehbaghi and M. Fujita, “Formal Verification Guided Automatic　Design Error Diagnosis and Correction of Complex Processors,” Proc. of 16th IEEE High Level Design Validation and Test Workshop, pp. 121-127, Nov. 2011.
A.M. Gharehbaghi and M. Fujita, “Post-Silicon Debugging of Many-Core Systems by Identifying Execution Paths Through Constraint Refinement,” International Workshop on Constraints in Formal Verification, Nov. 2011.
M. Fujita, “Accelerating Tsunami simulation with FPGA and GPU through automatic compilation,” International Conference on Wireless Technologies for Humanitarian Relief, Dec. 2011.
R. Krishnamoorthy, M. Fujita, K. Varadarajan, and S K Nandy, “Interconnect-topology independent mapping algorithm for a Coarse Grained Reconfigurable Architecture,” Proc. of International Conference on Field-Programmable Technology 2011, pp. 1-5, Dec. 2011.
M. Fujita and H. Yoshida, “Post-Silicon Patching for Verification/Debugging with High-Level Models and Programmable Logic,” Proc. of 17th Asia and South Pacific Design Automation Conference, pp. 232-237, Jan. 2012.
Y. Yang, A. Veneris, N. Nicolici, and M. Fujita, “Automated Data Analysis Techniques for a Modern Silicon Debug Environment,” Proc. of 17th Asia and South Pacific Design Automation Conference, pp. 298-303, Jan. 2012.
H. Mangassarian, H. Yoshida, A. Veneris, S. Yamashita, and Masahiro Fujita, “On Error Tolerance and Engineering Change with Partially Programmable Circuits,” Proc. of 17th Asia and South Pacific Design Automation Conference, pp. 695 - 700, Jan. 2012.
M. Fujita and H. Yoshida, “Post-silicon Debugging Targeting Electrical Errors with Patchable Controllers,” ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Feb. 2012.
A.M. Gharehbaghi and M. Fujita, “Transaction-Based Post-Silicon Debug of Many-Core System-on-Chips,” Proc. of International Symposium on Quality Electronic Design, pp. 703-709, Mar. 2012.

国内会議 Domestic Conference Papers

福井啓, 藤田昌宏, “FPGAを用いたSmith-Waterman Algorithmの高速化,” 電子情報通信学会技術研究報告, Vol. 111, No. 31, pp. 67-72, 2011年5月.
福井啓, 藤田昌宏, “高位合成ツールを利用したハードウエアアルゴリズムの最適化,” 情報処理学会研究報告, Vol. 2011-SLDM-150, No. 10, pp. 1-6, 2011年5月.
清水修一, 松本剛史, 藤田昌宏, “形式的検証を用いたプロセッサエラー回復機構の耐性評価手法の検討,” 情報処理学会研究報告, Vol. 2011-SLDM-150, No. 11, pp. 1-6, 2011年5月.
原田裕基, 松本剛史, 藤田昌宏, “反例と設計分割に基づく高位設計に対する効率的な設計修正支援手法,” Vol. 2011-SLDM-150, No. 12, pp. 1-6, 2011年5月.
李在城, 松本剛史, 藤田昌宏, “論理関数の充足不可能性に注目した論理回路デバッグ手法の検討,” 情報処理学会研究報告, Vol. 2012-SLDM-155, No. 5, pp. 1-6, 2012年3月.
吉田浩章, 藤田昌宏, “動作レベル・レジスタ転送レベル混在設計記述向け高位合成手法,” 電子情報通信学会技術研究報告, Vol. 111, No. 450, pp. 49-54, 2012年3月.

その他 Others

西原祐, “Formal Verification of High-Level Design Based on Control/Data Separation,” 情報処理学会誌情報処理, 研究会推薦博士論文速報, Vol. 52, No. 10, p. 1303, 2011年10月.
李蓮福, “エラートレース解析に基づくVLSI設計のデバッグ支援,” 情報処理学会誌情報処理, 研究会推薦博士論文速報, Vol. 53, No. 3, p. 275, 2012年3月.

2010

論文誌 Journal Papers

B. Alizadeh, M. Mirzaei, and M. Fujita, “Coverage Driven High Level Test Generation using a Polynomial Model of Sequential Circuits,” IEEE Transactions on Computer-Aided-Design of Integrated Circuits and Systems, Vol. 29, No. 5, pp. 737-748, May 2010.
B. Alizadeh and M. Fujita, “Modular Data-path Optimization and Verification Based on Modular-HED,” IEEE Transactions on Computer-Aided-Design of Integrated Circuits and Systems , Vol. 29, No. 9, pp. 1422-1435, Sep. 2010.
H. Yoshida and M. Fujita, “Performance-Constrained Transistor Sizing for Different Cell Count Minimization,” IPSJ Journal of Information Processing, Vol. 18, pp. 252-262, Dec. 2010.
H. Yoshida and M. Fujita, “Exact Minimum Factoring of Incompletely Specified Logic Functions via Quantified Boolean Satisfiability,” IPSJ Transactions on System LSI Design Methodology, Vol. 4, pp. 70-79, Feb. 2011.

国際会議 International Conference Papers

A.M. Gharehbaghi, M. Fujita, “Extracting Global Transaction orders from Local Ordering Information in Network-on-Chips,” E-Digest of 4th Workshop on Diagnostic Services in Network-on-Chips (DSNOC’10), pp. 249-262, Anaheim, California, USA, June 2010.
Y. Lee, T. Matsumoto, and M. Fujita, “Generation of I/O Sequences for a High-level Design from Those in Post-silicon for Efficient Post-silicon Debugging,” Proc. of 28th IEEE International Conference on Computer Design, pp. 402-408, Oct. 2010.
S. Yamashita, H. Yoshida and M. Fujita, “Increasing Yield Using Partially-Programmable Circuits,” Proc. of Workshop on Synthesis And System Integration of Mixed Information technologies, pp. 237-242, Oct. 2010.
R. Krishnamoorthy, K. Varadarajan, G. Garga, M. Alle, R. Narayan, S.K. Nandy, and M. Fujita, “Towards Minimizing Reconfiguration Overhead in Dynamically Reconfigurable Processors: REDEFINE as a case study”, Proc. Of the 2010 International Conference on Compilers, Architectures and Synthesis for Embedded Systems (CASES ’10), pp.77-86, Oct. 2010.
F. Haedicke, B. Alizadeh, G. Fey, M. Fujita, and R. Drechsler, “A Polynomial Datapath Optimization using Constraint Solving and Formal Modeling,” Proc. of the 2010 International Conference on Computer-Aided Design, pp. 756-761, Nov. 2010.
B. Alizadeh and M. Fujita, “A Debugging Method for Repairing Post-Silicon Bugs of High Performance Processors in the Fields,” Proc. of the 2010 International Conference on Field-Programmable Technology, pp. 328-331, Dec. 2010.
M. Fujita, B. Alizadeh, H. Yoshida and T. Matsumoto, “Post-silicon debugging with high level design descriptions and programmable controllers,” International Workshop on Microprocessor Test and Verification, Dec. 2010.
M. Fujita, H. Yoshida and J.-H. Lee, “Low Power Programmable Controllers for Reliable and Flexible Computing,” IEEE International Workshop on Reliability Aware System Design and Test, pp. 19-24, Jan. 2011.
S. Ono, H. Yoshida and M. Fujita, “A Scalable Heuristic for Incremental High-Level Synthesis and Its Application to Reliable Computing,” IEEE International Workshop on Reliability Aware System Design and Test, pp. 54-59, Jan. 2011.
M. Fujita, “Utilizing high level design information to speed up post-silicon debugging,” Proc. of Asia and South Pacific Design Automation Conference, pp. 301-305, Jan. 2011.
Y. Lee, T. Matsumoto, and M. Fujita, “On-chip Dynamic Signal Sequence Slicing for Efficient Post-Silicon Debugging,” Proc. of Asia and South Pacific Design Automation Conference, pp. 719-724, Jan. 2011.
A.M. Gharehbaghi, M. Fujita, “Global Transaction Ordering in Network-on-Chips for Post-Silicon Validation”, International Symposium on Quality Electronic Design (ISQED’11), pp. 284-289, Mar. 2011.
B. Alizadeh, and M. Fujita, “Debugging and Optimizing High Performance Superscalar Out-of-Order Processors Using Formal Verification Techniques”, International Symposium on Quality Electronic Design (ISQED), 2011, pp. 297-302.
R. Krishnamoorthy, K. Varadarajan, M. Fujita, S.K. Nandy, M. Alle, and R. Narayan, “Dataflow Graph Partitioning for Optimal Spatio-Temporal Computation on a Coarse Grained Reconfigurable Architecture,” Proc. 7th International Symposium on Applied Reconfigurable Computing (ARC 2011), pp. 125-132, March 2011.

国内会議 Domestic Conference Papers

原田裕基, 西原佑, 松本剛史, 藤田昌宏, “充足可能性判定に基づくシステムレベルデバッグ支援手法におけるバグモデルの導入による効率化,” 情報処理学会研究報告, Vol. 2010-SLDM-145, No. 10, pp. 1-6, 2010年5月.
Y. Lee, T. Matsumoto, and M. Fujita, “An I/O Sequence Slicing Method for Post-silicon Debugging,” 電子情報通信学会技術研究報告, Vol. 110, No. 106, pp. 31-36, 2010年6月.
吉田浩章, 藤田昌宏, “製造後機能修正可能な高電力効率アクセラレータの高位設計手法,” 情報処理学会 DAシンポジウム2010 論文集, pp. 45-50, 2010年9月.
Jiayi Zhang, Masahiro Fujita, “Automatic Interface Synthesis Between Incompatible Protocols with Advanced Features,” DAシンポジウム2010論文集, pp.27-32, 2010年9月.
松本剛史, 瀬戸謙修, 藤田昌宏, “ループ最適化に対する形式的等価性検証手法,” DAシンポジウム2010論文集, pp.105-110, 2010年9月.
李在浩, 吉田浩章, 藤田昌宏, “プログラマブルアクセラレータ向け制御回路方式の検討,” DAシンポジウム2010論文集, pp.183-188, 2010年9月.
吉田浩章, 藤田昌宏, “動的パッチ読み出し機構を備えた製造後機能修正可能アクセラレータ,” 情報処理学会研究報告, Vol. 2010-SLDM-146, No. 6, pp. 31-36, 2010年10月.
吉田浩章, 藤田昌宏, “仮想マルチプロセッサモデルに基づく高速SoCプロトタイピング手法,” 電子情報通信学会技術研究報告, Vol. 110, No. 316, pp. 7-12, 2010年11月.
小野翔平, 吉田浩章, 藤田昌宏, “発見的解法に基づくスケーラブルなインクリメンタル高位合成手法,” 電子情報通信学会技術研究報告, Vol. 110, No. 316, pp. 13-18, 2010年11月.
谷田英生, 吉田浩章, 藤田昌宏, 高性能SoCプロトタイプのFPGA実装方式の検討 , 電子情報通信学会技術研究報告, Vol. 110, No. 316, pp. 79-84, 2010年11月.
G. Di Guglielmo, M. Fujita, F. Fummi, G. Pravadelli, S. Soffia, “EFSM-based weight-oriented concolic testing for embedded software,” 情報処理学会研究報告, Vol. 2010-SLDM-147, No. 4, pp. 1-6, 2010年11月.
松本剛史, 藤田昌宏, “上位設計記述の解析を利用した製造後機能テストの効率化,” 情報処理学会研究報告, Vol. 2010-SLDM-147, No. 10, pp. 1 -6, 2010年11月.
吉田浩章, 藤田昌宏, “インクリメンタル高位合成に向けた設計記述間差分の計算手法,” 情報処理学会研究報告, Vol. 2011-SLDM-149, No. 21, pp. 1-6, 2011年3月.

2009

学会誌 Journal Papers

A. Mathur, M. Fujita, E. M. Clarke, and P. Urard, “Functional Equivalence Verification Tools in High-Level Synthesis Flows”, IEEE Design & Test of Computers, Vol.26, No.4, pp.88-95, July 2009.

論文誌 Journal Papers

O. Sarbishei, M. Tabandeh, B. Alizadeh, and M. Fujita, “A Formal Approach for Debugging Arithmetic Circuits”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol.28, No.5, pp.742-754, May 2009.
T. Nishihara, T. Matsumoto, and M. Fujita, “Word-Level Equivalence Checking in Bit-Level Accuracy with Identical Datapath”, IEICE Trans. on Information and Systems, Vol.E92-D, No.5, pp.972-984, May 2009.
B. Alizadeh and M. Fujita, “A Unified Framework for Equivalence Verification of Datapath Oriented Applications”, IEICE Trans. on Information and Systems, Vol.E92-D, No.5, pp.985-994, May 2009.
S. Gao, H. Yoshida, K. Seto, S. Komatsu, and M. Fujita, “Interconnect-aware pipeline synthesis for array based architectures”, IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, Vol.E92-A, No.6, pp.1464-1475, June 2009.
T. Matsumoto, T. Nishihara, and M. Fujita, “Performance Estimation with Automatic False-Path Detection for System-Level Designs”, IPSJ Transactions on System LSI Design Methodology, Vol.3, pp.69-80, Feb. 2010.

国際会議 International Conference Papers

B. Alizadeh and M. Fujita, “Modularity in Word-level Decision Diagrams”, Reed-Muller Workshop, pp.33-41, May 2009.
O. Sarbishei, B. Alizadeh, and M. Fujita, “A Debug Methodology for Arithmetic Circuits Based on Horner Expansion Diagram”, Proc. of 6th International Workshop on Constraints in Formal Verification, pp.30-45, June 2009.
O. Sarbishei, M. Tabandeh, B. Alizadeh, and M. Fujita, “High-level Optimization of Integer Multipliers over a Finite Bit-Width with Verification Capabilities”, Proc. of 7th International Conference on Formal Methods and Models for Codesign, pp.56-65, July 2009.
T. Matsumoto, T. Nishihara, Y. Kojima, and M. Fujita, “Equivalence Checking of High-Level Designs Based on Symbolic Simulation”, Proc. of 2009 International Conference on Communications, Circuits and Systems, pp.1129-1133, July 2009.
H. Yoshida and M. Fujita, “Rule-based Equivalence Checking of System-level Design Descriptions”, Proc. of International Conference on Communications, Circuits and Systems, pp.1139-1143, July 2009.
O. Sarbishei, B. Alizadeh, and M. Fujita, “Polynomial Datapath Optimization using Partitioning and Compensation Heuristics”, Proc. of the 46th Annual Design Automation Conference, pp.931-936, July 2009.
A.M. Gharehbaghi and M. Fujita, “Transaction-Based Debugging of System-on-Chips with Patterns”, Proc. of 27th IEEE International Conference on Computer Design, pp.186-192, Oct. 2009.
A.M. Gharehbaghi and M. Fujita, “On-Chip Transaction Level Debug Support for System-on-Chips”, Proc. of International SoC Design Conference, pp.124-127, Nov. 2009.
B. Alizadeh and M. Fujita, “Modular Arithmetic Decision Procedure with Auto-correction Mechanism”, Proc. of International High Level Design, Validation and Test Workshop, pp.138-145, Nov. 2009.
B. Alizadeh and M. Fujita, “Improved Heuristics for Finite Word-Length Polynomial Datapath Optimization”, Proc. of International Conference on Computer-Aided Design, pp.169-174, Nov. 2009.
Y. Lee, T. Nishihara, T. Matsumoto, and M. Fujita, “A Post-Silicon Debug Support Using High-level Design Description”, Proc. of the 18th Asian Test Symposium, pp.141-147, Nov. 2009.
H. Yoshida, S. Morishita, and M. Fujita, “Demonstration of Hardware Accelerated Formal Verification”, Proc. of International Conference on Field-Programmable Technology, pp.380-383, Dec. 2009.
B. Alizadeh and M. Fujita, “Optimization of Modular Multiplication on FPGA using Don’t Care Conditions”, Proc. of International Conference on Field-Programmable Technology, pp.399-402, Dec. 2009.
B. Alizadeh and M. Fujita, “Guided Gate-level ATPG for Sequential Circuits using a High-level Test Generation Approach”, Proc. of 15th Asia and South Pacific Design Automation Conference, pp.425-430, Jan. 2010.
A.M. Gharehbaghi, B. Alizadeh, and M. Fujita, “Aggressive Overclocking Support using a Novel Timing Error Recovery Technique on FPGAs”, Proc. of Eighteenth ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, page 288, Feb. 2010.
B. Alizadeh, A. M. Gharehbaghi, and M. Fujita, “Pipelined Microprocessors Optimization and Debugging”, Proc. of 6th International Symposium on Applied Reconfigurable Computing, pp.435-444, March 2010.
M. Fujita, H. Tanida, F. Gao, T. Nishihara, and T. Matsumoto, “Synthesis and Formal Verification of On-Chip Protocol Transducers through Decomposed Specification”, Proc. pf 11th International Symposium on Quality Electronic Design, pp.515-524, March 2010.

国内会議 Domestic Conference Papers

西原佑, 松本剛史, 藤田昌宏, “HW/SW協調設計の形式的検証における同期点の抽出による効率的な状態削減手法”, DAシンポジウム2009論文集, pp.49-54, 2009年8月.
藤田昌宏, “C言語ベース設計に対する高位設計検証技術”, DAシンポジウム2009論文集, pp.199-204, 2009年8月.
山下茂, 吉田浩章, 藤田昌宏, “Increasing Yield Using Partially-Programmable Circuits”, 電子情報通信学会技術研究報告, Vol.109, No.315, pp.125-130, 2009年12月.
吉田浩章, 藤田昌宏, “設計固有セルライブラリの自動生成手法”, 電子情報通信学会技術研究報告, Vol.109, No.315, pp.179-184, 2009年12月.
谷田英生, Mukul R. Prasad, Sreeranga P. Rajan, 藤田昌宏, “動的ウェブアプリケーションのクライアントを使用した網羅的検証手法”, 第6回ディペンダブルシステムシンポジウムDSS2009論文集, pp.82-93, 2009年12月.
R. Krishnamoorthy, K. Varadarajan, M. Alle, R. Narayan, M. Fujita, and S K Nandy, “Reducing Scheduling Overheads in Dynamically Reconfigurable Processors”, 電子情報通信学会技術研究報告, Vol.109, No.395, pp.7-12, 2010年1月.
Y. Lee, T. Nishihara, T. Matsumoto, and M. Fujita, “A Method of Reproducing Iuput/Ouput Error Trace on High-level Design for Hardware Debug Support”, 電子情報通信学会技術研究報告, Vol.109, No.406, pp.30-35, 2010年2月.
原田裕基, 西原佑, 松本剛史, 藤田昌宏, “ワードレベル論理式の充足可能性判定問題を利用したシステムレベル設計デバッグ支援手法”, 情報処理学会創立50周年記念(第72回)全国大会, pp.1-459-1-460, 2010年3月.
田川貴聡, 松本剛史, 藤田昌宏, “動作合成された束データ方式による非同期式回路とその動作仕様に対する等価性検証手法”, 情報処理学会創立50周年記念(第72回)全国大会, pp.1-153-1-154, 2010年3月.
谷田英生, Mukul R. Prasad, Sreeranga P. Rajan, 藤田昌宏, “動的ウェブアプリケーションの操作に対する画面間遷移の網羅的検証”, 情報処理学会創立50周年記念(第72回)全国大会, pp.1-459-1-460, 2010年3月.
吉田浩章, 藤田昌宏, “潜在的多様性を考慮したプログラマブルハードウェアの高位合成手法”, 電子情報通信学会技術研究報告, Vol.109, No.462, pp.67-72, 2010年3月.

2008

論文誌 Journal Papers

M. Fujita, K. Seto, and T. Sakunkonchak, “Dependence Graph Based Verification and Synthesis of Hardware/Software Co-Designs with SAT Related Formulation”, Journal on Satisfiability, Boolean Modeling and Computation, Vol.5, pp.57-82, June 2008.
M. Fujita, “Trends in Formal Verification Techniques for C-based Hardware Designs”, IPSJ Transactions on System LSI Design Methodology, Vol.2, pp.2-17, Feb. 2009.

国際会議 International Conference Papers

M. Fujita, T. Matsumoto, and H. Yoshida, “A HW/SW Co-Reuse Methodology Based on Design Refinement Templates in UML Diagrams”, Prof. on Third International Conference on Software and Data Technologies, Vol.SE, pp.240-245, Apr. 2008.
G. Fey, S. Komatsu, Y. Furukawa, and M. Fujita, “Targeting Leakage Constraints during ATPG”, Proc. of 5th IEEE International Workshop on Silicon Debug and Diagnosis (SDD08), pp.225-230, Apr. 2008.
D. Ando, T. Nishihara, T. Matsumoto, and M. Fujita, “Performance Estimation with Automatic False-Path Detection for System-Level Designs”, Proc. of International Workshop on Logic and Synthesis, pp.15-22, June 2008.
H. Yoshida, S. Morishita, and M. Fujita, “Hardware Accelerated Formal Verification”, Proc. of International Workshop on Logic and Synthesis, pp.247-252, June 2008.
O. Sarbishei, B. Alizadeh, and M. Fujita, “Arithmetic Circuits Verification without Looking for Internal Equivalences”, Proc. of IEEE International Conference on Formal Methods and Models for Codesign, pp.97-104, June 2008.
Y. Lee, Y. Ishikawa, T. Nishihara, Y. Kojima, T. Matsumoto, H. Yoshid, H. Yomiya, and M. Fujita, “UML-based specification level design and property checking methodology of SoC”, Proc. of UML-Workshop in Design Automation Conference, pp. 25-30, June 2008.
B. Alizadeh and M. Fujita, “Modular-HED: A Canonical Decision Diagram for Modular Equivalence Verification of Polynomial Functions”, Proc. of 5th International Workshop on Constraints in Formal Verification, pp.22-40, Aug. 2008.
T. Nishihara, T. Matsumoto, and M. Fujita, “Multi-Level Bounded Model Checking to Detect Bugs Beyond the Bound”, Proc. of IEEE International High Level Design Validation and Test Workshop, pp.49-55, Nov. 2008.
Y. Kojima, T. Nishihara, T. Matsumoto, and M. Fujita, “An Interactive Verification and Debugging Environment by Concrete/Symbolic Simulations for System-level Designs”, Proc. of The 17th Asian Test Symposium, pp.315-320, Nov. 2008.
G. Fey, S. Komatsu, Y. Furukawa, and M. Fujita, “Targeting Leakage Constraints during ATPG”, Proc. of 17th Asian Test Symposium (ATS'08), pp. 225-230, Nov. 2008.
Y. Kojima, T. Nishihara, T. Matsumoto, and M. Fujita, “FLEC: A Framework for System-level Debugging Support, Formal Verification and Static Analysis”, Proc. of The 15th Workshop on Synthesis and System Integration of Mixed Information Technologies, pp.341-346, March 2009.
S. Gao, T. Matsumoto, H. Yoshida, and M. Fujita, “Equivalence Checking of Loops Before and After Pipelining by Applying Symbolic Simulation and Induction”, Proc. of The 15th Workshop on Synthesis and System Integration of Mixed Information Technologies, pp.380-385, March 2009.
H. Yoshida and M. Fujita, “Improving the Accuracy of Rule-based Equivalence Checking of System-level Design Descriptions by Identifying Potential Internal Equivalences”, Proc. of IEEE International Symposium on Quality Electronic Design, pp.360-370, Mar. 2009.

国内会議 Domestic Conference Papers

西原佑, 松本剛史, 藤田昌宏, “プロパティ分割と限定モデル検査を利用した長い反例を持つ設計誤りの検出方法”, DAシンポジウム論文集, pp.121-126, 2008年8月.
吉田浩章, 藤田昌宏, “内部等価点の推定によるルールベース高位検証の高精度化”, 電子情報通信学会技術研究報告, Vol.108, No.298, pp.109-114, 2008年11月.
松本剛史, 李蓮福, 吉田浩章, 余宮尚志, 藤田昌宏, “反例を利用した網羅性の高いプロパティ集合生成手法”, 電子情報通信学会技術研究報告, Vol.108, No.298, pp.115-120, 2008年11月.
許金美, 西原佑, 松本剛史, 藤田昌宏, “順序回路の上位設計記述における等価性指定の自動化手法”, 電子情報通信学会技術研究報告, Vol.108, No.412, pp.105-110, 2009年1月.
高飛, 西原佑, 松本剛史, 藤田昌宏, “仕様から自動生成されたプロパティによるプロトコル変換機の形式的検証手法”, 電子情報通信学会技術研究報告, Vol.108, No.412, pp.111-116, 2009年1月.
李蓮福, 松本剛史, 藤田昌宏, “上位設計記述におけるダイナミックプログラムスライシングを用いたポストシリコンデバッグ支援手法”, 電子情報通信学会技術研究報告, Vol.108, No. 463, pp.31-36, 2009年3月.
原田裕基, 西原佑, 松本剛史, 藤田昌宏, “システムレベル設計における並列動作の同期に関するデバッグ支援手法”, 電子情報通信学会技術研究報告, pp. 37-42, 2009年3月.
田川貴聡, 吉田浩章, 藤田昌宏, “チップ内プログラマブル配線向け形式的検証手法”, 電子情報通信学会技術研究報告, Vol.108, No.478, pp.95-100, 2009年3月.
谷田英生, 吉田浩章, 松本剛史, 藤田昌宏, “リンク長及びレイテンシ制約下でのネットワークオンチップのトポロジ自動生成”, 電子情報通信学会技術研究報告, Vol.108, No.478, pp.129-134, 2009年3月.

2007

論文誌 Journal Papers

T. Nishihara, T. Matsumoto, S. Komatsu, M. Fujita, “Formal Verification of Hardware/Software Co-designs with Translation into Representations in State Transitions, Electronics and Communications in Japan, Part 2 Electronics, Vol.9, No.7, pp.11-19, July 2007.
S. Sasaki, T. Nishihara, D. Ando, M. Fujita, “Hardware/Software Co-design and Verification Methodology from System Level Based on System Dependence Graph, Journal of Universal Computer Science, Vol.13, No.13, pp.1972-2001, 2007.

国際会議 International Conference Papers

T. Sakunkonchak, T. Matsumoto, H. Saito, S. Komatsu, and M. Fujita, “Equivalence Checking in C-based System-Level Design by Sequentializing Concurrent Behaviors”, Proc. of IASTED International Conference on Advances in Computer Science and Technology, pp.36-42, April 2007.
T. Nishihara, D. Ando, T. Matsumoto, M. Fujita, “ExSDG: Unified Dependence Graph Representation of Hardware Design from System Level down to RTL for Formal Analysis and Verification”, Proc. of the International Workshop of Logic and Synthesis, pp.83-90, May 2007.
B. Alizadeh, M. Fujita, “A Hybrid Approach for Equivalence Checking Between System Level and RTL Descriptions”, Proc. of the International Workshop of Logic and Synthesis, pp.298-304, May 2007.
S. Gao, K. Seto, S. Komatsu, M. Fujita, “Interconnect-aware Pipeline Synthesis for Array based Reconfigurable Architectures”, Proc. of International Embedded Systems Symposium 2007, pp.121-134, May 2007.
Y. Lee, Y. Ishikawa, S. Kang, G. Park, S. Watanabe, K. Seto, S. Komatsu, H. Hamamura, M. Fujita, “UML-based Specification Method of Hardware IPs for Efficient IP Reuse”, Proc. of International UML-SoC Workshop at Design Automation Conference, pp.23-30, June 2007.
B. Alizadeh, M. Fujita, “LTED: A Canonical and Compact Hybrid Word-Boolean Representation as a Formal Model for Hardware/Software Co-designs”, Proc. of 4th Workshop on Constraints in Formal Verification, pp. 15-29, 2007.
B. Alizadeh, M. Fujita, “Automatic Merge-point Detection for Sequential Equivalence Checking of System-level and RTL Descriptions”, Proc. of 5th International Symposium on Automated Technology for Verification and Analysis, pp.129-144, Oct. 2007.
T. Sakunkonchak, S. Komatsu, M. Fujita, “Using Counterexample Analysis to Minimize the Number of Predicates for Predicate Abstraction”, Proc. of 5th International Symposium on Automated Technology for Verification and Analysis, pp.553-563, Oct. 2007.
B. Alizadeh, M. Fujita, “A Novel Formal Approach to Generate High-level Test Vectors without ILP and SAT Solvers”, Proc. of IEEE International Workshop on High Level Design Validation and Test, pp.97-104, Nov. 2007.
S. Komatsu, H. Yoshida, M. Fujita, “High-Level VLSI Design Methodology”, G-COE 2007 Workshop between National Chiao Tung University & The University of Tokyo, Dec. 2007.
M. Fujita, Y. Kojima, T. Matsumoto, T. Nishihara, D. Ando, “Static Checking and Formal Verification Using ExSDGs for Reliable System-Level SoC Designs”, Proc. of International Symposium on Secure-Life Electronics, pp.441-447, March 2008.
M. Fujita, H. Yoshida, S. Gao, Y. Lee, Y. Ishikawa, “System-Level Design Methodology for Next-Generation System-on-Chips”, Proc. of International Symposium on Secure-Life Electronics, pp.449-455, March 2008.
H. Yoshida, M. Fujita, “Performance-Constrained Different Cell Count Minimization for Continuously-Sized Circuits”, Proc. of Design, Automation & Test in Europe, pp.1099-1102, March 2008.

国内会議 Domestic Conference Papers Domestic Conference Papers

石川悠司, 小松聡, 藤田昌宏, “IP 再利用のためのプロトコル変換器自動合成”, 第9回組込みシステム技術に関するサマーワークショップ(SWEST9), pp.92-95, 2007年8月.
石川悠司, 小松聡, 藤田昌宏, “IP 再利用のための動的再構成可能プロトコル変換器合成手法”, 電子情報通信学会技術研究報告, Vol.107, No.225, pp.53-58, 2007年9月.
Y. Lee, Y. Ishikawa, Y. Kojima, H. Yoshida, H. Yomiya, and M. Fujita, “Specification description and high-level design methodology of SoC considering design reuse”, 電子情報通信学会技術研究報告, Vol.107, No.505, pp.55-60, 2008年3月.
石川悠司, 小松聡, 藤田昌宏, “積グラフ探索を利用した実用的なプロトコル変換器の自動合成と検証”, 電子情報通信学会技術研究報告, Vol.107, No.506, pp.1-6, 2008年3月.
安藤大介, 松本剛史, 西原佑, 藤田昌宏, “システムレベル設計言語に対するフォールスパスを考慮した性能評価”, 電子情報通信学会技術研究報告, Vol.107, No.507, pp.49-54, 2008年3月.
森下賢志, 吉田浩章, 藤田昌宏, “準形式的モデル検査のハードウェア実装による高速化の検討”, 電子情報通信学会技術研究報告, Vol.107, No.558, pp.115-120, 2008年3月.
小島慶久，西原佑，松本剛史，藤田昌宏, “システムレベル設計記述に対する具体値・記号値混合シミュレーションによる入力パターンの自動生成手法”, 電子情報通信学学会技術研究報告, Vol.107, No.558, pp.133-138, 2008年3月.

2006

論文誌 Journal Papers

Y. Liu, S. Komatsu, M. Fujita, “Synchronization Mechanism of Timed/Untimed Mixed-Signal System Level Design Environment”, IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, Vol.E89-A, No.4, pp.1018-1026, Apr. 2006.
西原佑, 松本剛史, 小松聡, 藤田昌宏, “状態遷移表現への変換に基づくハードウェア/ソフトウェア協調設計の形式的検証手法”, 電子情報通信学会論文誌, 第J89-D巻, 第4号, pp.651-659, 2006年4月.
Y. Liu, S. Komatsu, M. Fujita, “The AMS Extension to System Level Design Language ---SpecC”, IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, Vol.E89-A, No.12, pp.3397-3407, Dec. 2006.
T. Sakunkonchak, S. Komatsu, M. Fujita, “Synchronization Verification in System-Level Design with ILP Solvers”, IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, Vol.E89-A, No.12, pp.3387-3396, Dec. 2006.

国際会議 International Conference Papers

S. Komatsu, M. Fujita, “An Optimization of Bus Interconnects Pitch for Low-Power and Reliable Bus Encoding Scheme”, Proc. of 2006 IEEE International Symposium on Circuits and Systems, pp.1723-1726, May 2006.
S. Sasaki, T. Nishihara, M. Fujita, “Slicing-based Hardware/Software Co-design Methodology from Functional Specications”, Electronic Notes in Theoretical Computer Science, Vol.159, pp.265-280, May 2006.
S. Komatsu, M. Ikeda, K. Asada, “A New Trial on VLSI Test Exercise Course for Undergraduate/Graduate School in EE Department”, Proc. of 6th International Workshop on Microelectronics Education, pp.92-95, Jun. 2006.
Y. Ishikawa, S. Watanabe, K. Seto, M. Fujita, “Protocol Wrapper Generation from Statement Based Specification”, Proc. of International Workshop on Logic and Synthesis 2006, pp.118-125, June 2006.
S. Watanabe, K. Seto, Y. Ishikawa, S. Komatsu, M. Fujita, “Automatic Protocol Transducer Synthesis aiming at facilitating IP-Reuse”, Proc. of International Workshop on Logic and Synthesis 2006, pp.164-170, Jun. 2006.
D. Ando, T. Nishihara, S. Sasaki, T. Matsumoto, M. Fujita, “Design Error Detection in System-Level Designs by Dependence Analysis and Formal Checker”, Proc. of International Workshop on Logic and Synthesis 2006, pp.255-262, June 2006.
T. Nishihara, T. Matsumoto, M. Fujita, “Equivalence Checking with Rule-Based Equivalence Propagation and High-Level Synthesis”, Proc. of the International Workshop on High Level Design Validation and Test, pp.162-169, Nov. 2006.
S. Watanabe, Y. Ishikawa, K. Seto, S. Komatsu, M. Fujita, “Dynamically Reconfigurable Protocol Transducer”, Proc. of the International Conference on Field Programmable Technology 2006, pp.341-344, Dec. 2006.
S. Watanabe, K. Seto, Y. Ishikawa, S. Komatsu, M. Fujita, “Protocol Transducer Synthesis using Divide and Conquer Approach”, Proc. of The 12th Asia and South Pacific Design Automation Conference (ASPDAC2007), pp.280-285, Jan. 2007.
T. Matsumoto, D. Ando, T. Nishihara, M. Fujita, “Development and Verification of a Collaborative Printing Environment”, Proc. of the Fifth International Conference on Creating, Connecting and Collaborating through Computing, pp.95-102, Jan. 2007.

国内会議 Domestic Conference Papers Domestic Conference Papers

渡辺翔太, 瀬戸謙修, 石川悠司, 小松聡, 藤田昌宏, “設計再利用の為のプロトコル変換器合成手法”, 第19回回路とシステム軽井沢ワークショップ, pp.229-234, 2006年4月.
瀬戸謙修, 藤田昌宏, “メモリアクセスおよびリソース共有を行うカスタム命令自動生成手法”, 電子情報通信学会研究会研究報告 Vol.106, No.32, pp.19-24, 2006年5月.
Subash Shankar, 藤田昌宏, “ボトムアップ解析に基づくSpecC記述間の等価性検証”, 電子情報通信学会研究会研究報告 Vol.106, No.32, pp.1-6, 2006年5月.
松本剛史, 小松聡, 藤田昌宏, “動作合成前後の設計記述に対する記号シミュレーションによる形式的等価性検証の検討”, 電子情報通信学会技術研究報告, Vol.106, No.32, pp.7-12, 2006年5月.
瀬戸謙修, 藤田昌宏, “高位合成技術を利用したカスタム命令自動生成手法”, DAシンポジウム2006論文集, pp.49-54, 2006年7月.
西原佑, 松本剛史, 藤田昌宏, “高位合成を利用したデータパス抽象化に基づく等価性検証手法”, DAシンポジウム2006論文集, pp.151-156, 2006年7月.
松本剛史, Thanyapat Sakunkonchak, 齋藤寛, 小松聡, 藤田昌宏, “線形計画法を利用したシステムレベル設計での動作並列化前後での等価性検証手法”, DAシンポジウム論文集, pp.157-162, 2006年7月.
安藤大介, 西原佑, 松本剛史, 藤田昌宏, “依存解析と形式的検証によるCベース言語プログラムの誤り検出手法, 第8回組込みシステム技術に関するサマーワークショップ予稿集”, pp.99-106, 2006年7月.
安藤大介, 西原佑, 松本剛史, 藤田昌宏, “システムレベル設計に対する拡張システム依存グラフを利用した記述チェッカ”, 電子情報通信学会技術研究報告 Vol.106, No.547, pp.37-42, 2007年3月.
石川悠司, SeongWoon Kang, 李蓮福, GiLark Park, 渡邊翔太, 瀬戸謙修, 小松聡, 浜村博史, 藤田昌宏, “ハードウェア設計における設計資産の仕様記述およびその検証手法”, 電子情報通信学会技術研究報告, Vol.106, No.547, pp.43-48, 2007年3月.
李蓮福, GiLark Park, 石川悠司, SeongWoon Kang, 渡邊翔太, 瀬戸謙修, 小松聡, 浜村博史, 藤田昌宏, “設計再利用のためのIPライブラリ検索システム”, 電子情報通信学会技術研究報告, Vol.106, No.547, pp.49-54, 2007年3月.
松本剛史, 瀬戸謙修, 藤田昌宏, “C言語プログラムにおけるループ最適化に対するループ展開を伴わない等価性検証手法”, 電子情報通信学会技術研究報告, Vol.106, No.602, pp.55-60, 2007年3月.

2005

論文誌 Journal Papers

M. Fujita, “Equivalence checking between behavioral and RTL descriptions with virtual controllers and datapaths”, ACM TODAES, Vol.10, No.4, pp.610-626, Oct. 2005.
S. Komatsu, M. Fujita, “Low Power and Fault Tolerant Encoding Methods for On-Chip Data Transfer in Practical Applications”, IEICE Trans. on Fundamentals, Vol.E88-A, No.12, pp.3282-3289, Dec. 2005.
T. Matsumoto, H. Saito, M. Fujita, “An Equivalence Checking Method for C Descriptions Based on Symbolic Simulation with Textual Differences”, IEICE Trans. on Fundamentals, Vol.E88-A, No.12, pp.3315-3323, Dec. 2005.

国際会議 International Conference Papers

Y. Liu, T. Sakunkonchak, S. Komatsu, M. Fujita, “System Level Design Language Extensions for Timed/Untimed Digital-Analog Combined System Design”, Proc. of GLSVLSI, pp.130-133, Chicago, US, Mar. 2005.
M. Fujita, “Verification and synthesis of high level hardware designs with CSP/SAT based approaches”, 3rd International Workshop on Constraints in Formal Verification, Tallinn, Estonia, July 2005.
T. Matsumoto, H. Saito, M. Fujita, “Equivalence Checking for Transformations and Optimizations in C Programs on Dependence Graphs”, Proc. of International Workshop on Logic and Synthesis, pp.357-366, June 2005.
T. Sakunkonchak, S. Komatsu, M. Fujita, “Synchronization Verification in System-Level Design with ILP Solver”, Proc. of 3rd ACM-IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE 2005), pp.121-130, Verona, Italy, July 2005.
M. Fujita, “A Formal Design Approach from Software Oriented UML Descriptions to Hardware Oriented RTL”, Proc. of 3rd ACM-IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE 2005), pp.241-242, Verona, Italy, July 2005.
M. Fujita, S. Sasaki, K. Matsui, “Object-oriented Analysis and Design of Hardware/Software Co-designs with Dependence Analysis for Design Reuse”, Proc. of 2005 IEEE International Conference on Information Reuse and Integration, pp.318-325, Las Vegas, USA, Aug. 2005.
Y. Liu, S. Komatsu, M. Fujita, “AMS Extensions for Timed/Untimed System Level Design Language”, Proc. FDL'05, pp.77-80, Lausanne, Switzerland, Sep. 2005.
M. Fujita, “Behavior-RTL Equivalence Checking Based on Data Transfer Analysis with Virtual Controllers and Datapaths”, Proc. of 13th Correct Hardware Design and Verification Methods (CHARME 2005), pp.340-345, Saarbrucken, Germany, Oct. 2005.
S. Sasaki, T. Nishihara, M. Fujita, “Slicing-based Hardware/Software Co-design Methodology From Functional Specifications”, FSEN '05, pp.186--200, Oct. 2005.
S. Gao, K. Seto, S. Komatsu, M. Fujita, “Pipeline scheduling for array based reconfigurable architectures considering interconnect delays”, Proc. of 4th IEEE International Conference on Field Programmable Technologies, pp.137-144, Singapore, Dec. 2005.
M. Fujita, T. Nishihara, D. Ando, “System LSI distributed collaborative design environment for both designers and CAD developers/engineers”, Proc. of IEEE The Fourth International Conference on Creating, Connecting and Collaborating through Computing (C5 2006), Berkeley, USA, Jan. 2006.
K. Matsui, M. Fujita, “Object-Oriented analysis and specification for HW/SW co-design with UML diagrams”, Proc. of the IASTED International Conference on Advances in Computer Science and Technology (ACST 2006), pp.38-43, Puerto Vallarta, Mexico, Jan. 2006.
T. Matsumoto, H. Saito, M. Fujita, “Equivalence Checking of C Programs by Locally Performing Symbolic Simulation on Dependence Graphs”, Proc. of International Symposium on Quality Electronic Design, pp.370-375, Mar. 2006.

国内会議 Domestic Conference Papers

Y. Liu, S. Komatsu, M. Fujita, “Timed/Untimed Synchronization for Mixed-Signal System Level Design Environment”, 第18回回路とシステム軽井沢ワークショップ論文集, pp.551-556, 2005年4月.
松本剛史, 齋藤寛, 藤田昌宏, “Cベース高位設計における等価性検証フレームワークと反例解析手法の提案”, 第18回回路とシステム軽井沢ワークショップ論文集, pp.557-562, 2005年4月.
松本剛史, 齋藤寛, 藤田昌宏, “依存グラフを用いた局所的な記号シミュレーションによるC言語記述に対する等価性検証手法の提案”, 電子情報通信学会技術研究報告, Vol.508, No.58, pp.25-30, 2005年5月.
S. Gao, Y. Ishikawa, S. Watanabe, K. Seto, S. Komatsu, M. Fujita, “Pipeline Synthesis for Array Based Reconfigurable Architectures Considering Interconnect Delays”, DAシンポジウム2005, pp.225-230, 2005年8月.
西原佑, 松本剛史, 藤田昌宏, “長い反例のみを持つ設計誤りに対する帰納的推論を用いた検証手法”, 電子情報通信学会技術研究報告 Vol.105, No.644, pp.1-6, 2006年3月.
佐々木俊介, 西原佑, 安藤大介, 藤田昌宏, “SpecC言語の依存グラフを利用したプログラムチェッカ”, 電子情報通信学会技術研究報告, Vol.105, No.669, pp.13-18, 2006年3月.
石川悠司, 渡邊翔太, 瀬戸謙修, 藤田昌宏, “プロトコル表現効率化に基づくプロトコル変換器合成手法に関する研究”, 電子情報通信学会技術研究報告, Vol.105, No.669, pp.67-72, 2006年3月.
松井健, 小松聡, 藤田昌宏, “組込みシステムのシステムレベル設計におけるオブジェクト指向技術の応用”, 電子情報通信学会技術研究報告, Vol.105, No.669, pp.73-78, 2006年3月.

講演・チュートリアル等

A. Mathur, M. Fujita, M. Balakrishnan, R. Mitra, “Sequential equivalence checking”, 19th International Conference on VLSI Design, Hyderabad, India, Jan. 2006.

2004

論文誌 Journal Papers

小島慶久, 藤田昌宏, “分割二分決定グラフによる有限状態機械の到達可能性解析のPCクラスタを用いた並列実装手法の提案”, 情報処理学会論文誌, 第46巻, 第3号,　pp.803-815, 2005年3月.

国際会議 International Conference Papers

T. Matsumoto, H. Saito, M. Fujita, “An Efficient Equivalence Checking of Similar C Descriptions with Use of the Textual Difference”, Proc. of IEEE/ACM International Workshop on Logic and Synthesis, pp.314-320, June 2004.
K. Seto, Y. Kojima, M. Fujita, “Compiler Techniques for Field Modifiable Architectures”, Proc. of 2004 Workshop on Compilers and Tools for Constrained Embedded Systems, pp.58-66, Sep. 2004.
S. Komatsu, M. Fujita, “Low Power and Fault Tolerant Encoding Methods for On-Chip Data Transfer”, Proc. of the Workshop on Synthesis And System Integration of Mixed Information Technologies, pp.34-40, Oct. 2004.
T. Matsumoto, H. Saito, M. Fujita, “An Equivalence Checking Method for C Descriptions based on Symbolic Simulation with Textual Differences”, Proc. of IASTED International Conference on Advences in Computer Science and Technology, pp.246-251, Nov. 2004.
K. Tanabe, S. Sasaki, M. Fujita, “Program Slicing for System Level Designs in SpecC”, Proc. of IASTED International Conference on Advances in Computer Science and Technology, pp.252-258, Nov. 2004.

国内会議 Domestic Conference Papers

松本剛史, 齋藤寛, 藤田昌宏, “C言語動作記述の既存RTL用検証ツールを用いた検証の提案”, DAシンポジウム2004論文集, pp.241-146, 2004年7月.
小松聡, 藤田昌宏, “データ符号化によるVLSIにおける低消費電力・高信頼データ伝送手法の検討”, 電子情報通信学会技術研究報告 Vol.104, No.478, pp.185-190, 2004年12月.
Thanyapat Sakunkonchak, Satoshi Komatsu, Masahiro Fujita, “A Framework on Synchronization Verification of System-Level Design”, 電子情報通信学会技術研究報告 Vol.104, No.708, pp.71-76, 2005年3月.
佐々木俊介, 田辺健, 藤田昌宏, “SpecC記述のプログラムスライシングを利用した未初期化変数・未使用変数の検出”, 電子情報通信学会技術研究報告 Vol.104, No.708, pp.59-64, 2005年3月.
松井健, 小松聡, 藤田昌宏, “UMLとSpecCを用いたハードウェアの上位設計手法に関する検討”, 電子情報通信学会技術研究報告 Vol.104, No.708, pp.65-70, 2005年3月.
西原佑, 松本剛史, 小松聡, 藤田昌宏, “FSMへの変換に基づくHW/SW協調設計の形式的検証手法に関する研究”, 情報処理学会研究報告 Vol.2005, No.27, pp.37-42, 2005年3月.

2003

論文誌 Journal Papers

瀬戸謙修, 藤田昌宏, 浅田邦博, “充足可能性判定を利用した最適コード生成手法”, 情報処理学会論文誌, 第44巻, 第5号, pp.1202-1205, 2003年.
S. Komatsu, M. Fujita, “Irredundant Low Power Address Bus Encoding Techniques Based on Adaptive Codebooks”, IEICE Trans. Fundamentals, Vol.E86-A, No.12, pp.3001-3008, Dec. 2003.
T. Sakunkonchak, S. Komatsu, M. Fujita, “Verification of Synchronization in SpecC Description with the Use of Difference Decision Diagrams”, IEICE Trans. Fundamentals, Vol.E86-A, No.12, pp.3192-3199, Dec. 2003.

国際会議 International Conference Papers

K. Seto, M. Fujita, K. Asada, “Retargetable Code Generation Based on Finite State Machine and Boolean Satisfiability”, Proc. of IEEE/ACM International Workshop on Logic and Synthesis, pp.260-265, May 2003.
T. Matsumoto, H. Saito, M. Fujita, “Equivalence Checking of C-based Hardware Descriptions by Using Symbolic Simulation and Program Slicing”, Proc. of IEEE/ACM International Workshop on Logic and Synthesis, pp.252-259, May 2003.
T. Sakunkonchak, M. Fujita, “Formal Verification of Synchronization Issues in SpecC Description with Automatic Abstraction”, Proc. of International Conference on Dependable Systems and Networks (Workshop on Model-Checking for Dependable Software-Intensive Systems), pp.w67-w71, Jun. 2003.
T. Matsumoto, T. Sakunkonchak, H. Saito, M. Fujita, “Verificaiton of Behavioral Consistency in C by Using Symbolic Simulator and Program Slicer”, Proc. of International Conference on Dependable Systems and Networks (Workshop on Model-Checking for Dependable Software-Intensive Systems), pp.w80-w84, Jun. 2003.
H. Saito, K. Seto, Y. Kojima, S. Komatsu, M. Fujita, “Engineering Changes in Field Modifiable Architectures”, Proc. of International Conference on Formal Methods and Models for Co-Desgn, pp.87-94, Jun. 2003.
T. Sakunkonchak, M. Fujita, “Formal Verificaiton of Synchronization Issue in System-Level Design with Automatic Abstraction”, Proc. of IFIP International Conference on Very Large Scale Integration (Ph.D. Forum), p.464, Dec. 2003.
M. Fujita, S. Komatsu, T. Sakunkonchak, Y. Kojima, K. Tanabe, T. Matsumoto, “CAD Techniques for Hardware/Software Co-design Targeting Space Satellites”, Proc. of International Symposium on Electronics for Future Generations, pp.107-112, Mar. 2004.

国内会議 Domestic Conference Papers

松本剛史, 齋藤寛, 藤田昌宏, “Ｃ言語でのハードウェア記述に対する効率的な等価性検証手法の提案”, 電子情報通信学会技術研究報告 Vol.103, No.40, pp.31-36, 2003年5月.
小松聡, 石原亨, 藤田昌宏, “Ｃプログラムからのハードウェア設計教育 --Handel-CとDK1を使った演習--”, DA シンポジウム, pp.253-258, 2003年7月.
小松聡, 藤田昌宏, “LSI における検証技術, ソフトウェア工学の基礎ワークショップ”, pp.251-256, 2003年11月.
小島慶久, 瀬戸謙修, 齋藤寛, 小松聡, 藤田昌宏, “リコンフィギャラブルなブロック間接続をもつアーキテクチャの静的最適化のための高位合成手法”, 電子情報通信学会第2種研究会(第2回リコンフィギャラブルシステム研究会)技術研究報告, pp.16-21, 2003年11月.
瀬戸謙修, 藤田昌宏, 浅田邦博, “アプリケーションに特化した機能ユニットおよびコンフィギュレーション可能な接続からなるデータパス向けコンフィギュレーション生成手法”, 電子情報通信学会第2種研究会(第2回リコンフィギャラブルシステム研究会)技術研究報告, pp.34-39, 2003年11月.
松本剛史, 齋藤寛, 藤田昌宏, “Ｃ言語を対象とした記述間の差異に基づく効率的な等価性検証手法”, 電子情報通信学会技術研究報告 Vol.103, No.702, pp.61-66, 2004年3月.
田辺健, 齋藤寛, 小松聡, 藤田昌宏, “SpecC言語によるハードウェア・ソフトウェア混在システム記述を対象としたプログラムスライシング手法の提案”, 電子情報通信学会技術研究報告 Vol.103, No.702, pp.79-84, 2004年3月.
佐々木俊介, 小松聡, 藤田昌宏, “電子系・機械系協調設計における設計検証法に関する検討”, 電子情報通信学会技術研究報告 Vol.103, No.735, pp.27-32, 2004年3月.
松井健, 小松聡, 藤田昌宏, “UMLを用いた実時間・高信頼性組み込みシステムの上位設計についての検討”, 電子情報通信学会技術研究報告 Vol.103, No.735, pp.33-38, 2004年3月.

講演・チュートリアル等 Invited Talks & Tutorials

M. Fujita, “Application of Formal Method in Electronic Parts of Spece Satellite Designs”, International Conference on Dependable Systems and Networks (Workshop on Model-Checking for Dependable Software-Intensive Systems), Jun. 2003.
藤田昌宏, “高位検証技術”, 電子情報通信学会ソサイエティ大会, チュートリアル講演, 2003年9月.
M. Fujita, “System Level Design Methodologies from the Viewpoint of Formal Verification”, International Conference on ASIC, Tutorial, Oct. 2003.
藤田昌宏, “形式的検証ツールの実像と虚像”, システム LSI ワークショップ, デザインガイア, 2003年11月.
S. Komatsu, “Research and Education Activities of VDEC (VLSI Design and Education Center)”, Waseda University System LSI International Workshop, Jan. 2004.
I. Ghosh, M. Prasad, R. Mukherjee, M. Fujita, “High Level Design Validation: Current Practices and Future Directions”, International Conference on VLSI Design, Tutorial, Jan. 2004.
M. Fujita, D. Gajski, T. Imai, T. Hasegawa, “System-level Design Methodology for SoC Design”, Asia South Pacific Design Automation Conference, Tutorial, Jan. 2004.

2002

論文誌 Journal Papers

瀬戸謙修, 藤田昌宏, “有限状態機械 (FSM) とシンボリック状態探索を利用したコード生成手法”, 情報処理学会論文誌, 第43巻, 第5号, pp.1235-1251, 2002.

国際会議 International Conference Papers

F. Fallah, I. Ghosh, M. Fujita, “Coverage Metric for Observability-Based Validation of C Programs”, Proc. of IEEE International Workshop on Microprocessor Test and Verification, Jun. 2002.
Y. Kojima, H. Saito, K. Seto, S. Komatsu, M. Fujita, “Field Modifiable Architecture and Its Design Methodology -System Design Without Logic Synthesis-”, Proc. of IEEE/ACM International Workshop on Logic and Synthesis, pp.103-108, June 2002.
H. Saito, H. Nakamura, M. Fujita, T. Nanya, “Logic Optimization of Asynchronous Speed Independent Controllers by Using Transduction Method”, Proc. of IEEE/ACM International Workshop on Logic and Synthesis, pp.245-250, June 2002.
T. Sakunkonchak, M. Fujita, “Verification of Synchronization in SpecC Description with the Use of Difference Decision Diagrams”, Proc. of Forum on specification and Design Languages, Sep. 2002.
K. Seto, Y. Kojima, H. Saito, S. Komatsu, M. Fujita, “Field Modifiable Architecture and its Design Method”, ACM SIGPLAN Conference on Programming Language Design and Implementation, 2002.
H. Saito, T. Ogawa, T. Sakunkonchak, M. Fujita, T. Nanya, “An Equivalence Checking Methodology for Hardware Oriented C-based Specifications”, Proc. of IEEE International High Level Design Validation and Test Workshop, pp.139-144, Oct. 2002.
T. Sakunkonchak, M. Fujita, “Verification of Event-Based Synchronization of SpecC Description Using Difference Decision Diagrams”, International Conference on Formal Techniques for Networked and Distributed Systems, Nov. 2002.
M. Kubo, M. Fujita, “Debug Methodology for Arithmetic Circuits on FPGAs”, Proc. of IEEE International Conference on Field-Programmable Technology, pp.236-242, Dec. 2002.
S. Komatsu, Y. Kojima, H. Saito, K. Seto, M. Fujita, “Field Modifiable Architecture with FPGAs and its Design Methodology”, Proc. of IEEE International Conference on Field-Programmable Technology, pp.382-385, Dec. 2002.
M. Fujita, S. Komatsu, H. Saito, K. Seto, T. Sakunkonchak, Y. Kojima, “Field Modifiable Architecture with FPGAs and its Design/Verification/Debugging Methodologies”, Proc. of Annual Hawaii International Conference on System Sciences, p.279, Jan. 2003.
S. Komatsu, M. Fujita, “Irredundant Address Bus Encoding Techniques based on Adaptive Codebooks for Low Power”, Proc. Asia South Pacific Design Automation Conference, pp.9-14, Jan. 2003.
F. Fallah, I. Ghosh, M. Fujita, “Event-Driven Obsevability Enhanced Coverage Analysis of C Programs for Functional Validation”, Proc. of Asia South Pacific Design Automation Conference, pp.123-128, Jan. 2003.
H. Saito, H. Nakamura, M. Fujita, T. Nanya, “Logic Optimization of Asynchronous Speed Independent Controllers by Using Transduction Method”, Proc. of Asia South Pacific Design Automation Conference, pp.197-202, Jan. 2003.

国内会議 Domestic Conference Papers

小川貴也, 齋藤寛, 藤田昌宏, “Ｃ言語によるハードウェア記述に対する等価性検証手法”, DAシンポジウム, pp.131-136, 2002年7月.
Thanyapat Sakunkonchak, 藤田昌宏, “Verification of Synchronization in SpecC Descriptions Using Difference Dicision Diagram”, DAシンポジウム, pp.137-142, 2002年7月.
小松聡, 藤田昌宏, “低電力設計のための非冗長アドレスバス符号化手法の提案”, DAシンポジウム, pp.167-172, 2002年7月.
劉宇, 世羅元啓, 小松聡, 藤田昌宏, “Integration of Logic Optimization and Layout Processes by Using Rewriting Method”, DAシンポジウム, pp.217-222, 2002年7月.
小島慶久, 黒羽毅, 藤田昌宏, “専用プロセッサ用命令セットの自動生成手法の提案と実装”, 電子情報通信学会技術研究報告, Vol.102, No.73, pp.7-12, 2002年.
久保賢生, 藤田昌宏, “算術演算回路のデバッグ支援技術”, 電子情報通信学会技術研究報告, Vol.102, No.478, pp.79-84, 2002年11月.

2001

論文誌 Journal Papers

E. M. Clarke, M. Fujita, S. P. Rajan, T. Reps, S. Shankar, T. Teitelbaum, Program Slicing for VHDL, International Journal on Software Tools for Technology Transfer, Vol.4, No.1, pp.125-137, Springer-Verlag, Oct. 2001.

国際会議 International Conference Papers

H. Yoshida, M. Sera, M. Kubo, M. Fujita, Integration of Logic Synthesis and Layout Processes by Generating Multiple, Proc. of IEEE/ACM International Workshop on Logic and Synthesis, pp.196-200, Jun. 2001.
M. Kubo, M. Fujita, A Redesign Method Based on Evaluating Quatified Boolean Formulae, Proc. of IEEE/ACM International Workshop on Logic and Synthesis, pp.261-264, Jun. 2001.
S. Komatsu, M. Ikeda, K. Asada, Bus Data Encoding with Coupling-driven Adaptive Code-book Method for Low Power Data Transmission, Proc. of European Solid-State Circuits Conference, pp.312-315, Sep. 2001.
M. Fujita, H. Nakamura, The Standard SpecC Language, Proc. of International Symposium on System Synthesis, pp.81-86, Oct. 2001.

国内会議 Domestic Conference Papers

藤田昌宏, Indradeep Ghosh, レジスタ転送レベルの ATPG 手法を利用したＣ言語に基づくシステム記述の検証について, DAシンポジウム, pp.61-66, 2001年7月.
久保賢生, 藤田昌宏, Quantified SAT を利用した論理設計の再利用について, DAシンポジウム, pp.43-48, 2001年7月.
小松聡, 池田誠, 浅田邦博, 低消費電力データ転送のための配線間結合容量を考慮した適応型コード帳符号化方式の提案と評価, DAシンポジウム, pp.101-106, 2001年7月.

2000

論文誌 Journal Papers

I. Ghosh, M. Fujita, Automatic Test Pattern Generation for Functional Resister-Transfer Level Circuits Using Assignment Decision Diagrams, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol.20, No.3, pp.402-415, 2001.

国際会議 International Conference Papers

A. Jain, V. Boppana, R. Mukherjee, J. Jain, M. Fujita, M. Hsiao, Testing, Verification, and Diagnosis in the Presence of Unkowns, Proc. of IEEE VLSI Test Symposium, pp.263-269, Apr. 2000.
I. Ghosh, M. Fujita, Automatic Test Pattern Generation for Functional RTL Circuits Using Assignment Decision Diagrams, Proc. of ACM/IEEE Design Automation Conference, pp.43-48, June 2000.
D. W. Currie, A. J. Hu, S. Rajan, M. Fujita, Automatic Formal Verification of DSP Software, Proc. of ACM/IEEE Design Automation Conference, pp.130-135, June 2000.
Y. Lu, J. Jain, E. Clarke, M. Fujita, Efficient Veriable Ordering Using aBDD Based Sampling, Proc. of ACM/IEEE Design Automation Conference, pp.687-692, June 2000.
V. Boppana, S. Rajan, K. Takayama, M. Fujita, Sequential ATPG Techniques for Model Checking, Proc. of World Multiconference on Systemics, Cybernetics and Informatics, July 2000.
D. W. Currie, A. J. Hu, S. Rajan, M. Fujita, Semi-Formal Verification of Low-Level DSP Software, Proc. of World Multiconference on Systemics, Cybernetics and Informatics, July 2000.
M. Fujita, Boolean problems that have real application in CAD for digital systems, Proc. of International Workshop Boolean Problems, Sep. 2000.
M. Fujita, I. Ghosh, Automatic Test Bench Generation for Equivalence Checking of C Programs Based on ATPG Techniques, Proc. of International Workshop on Software and Compilers for Embedded Systems, Mar. 2001.
K. Seto, T. Kuroha, D. Nakatani, K. Asada, M. Fujita, Co-Design of Custom VLIW-DSP Type Data-path Architecture and its Parallel Program for Loops Based on Formal Verification Techniques, Proc. of International Workshop on Software and Compilers for Embedded Systems, Mar. 2001.