Publications

Journal Papers

  1. R. Ikeno, T. Maruyama, S. Komatsu, T. Iizuka, M. Ikeda, and K. Asada,
    “High-throughput Electron Beam Direct Writing of VIA Layers by Character Projection with One-dimensional VIA Characters,”
    accepted for publication in IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences.
  2. S. Gao, H. Yoshida, K. Seto, S. Komatsu, and M. Fujita,
    “Interconnect-Aware Pipeline Synthesis for Array-Based Architectures,”
    IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E92-A, No. 6, pp. 1464-1475, 2009.
  3. T. Nishihara, T. Matsumoto, S. Komatsu, M. Fujita,
    "Formal Verification of Hardware/Software Co-designs with Translation into Representations in State Transitions,"
    Electronics and Communications in Japan, Part 2 Electronics, Vol.9, No.7, pp.11-19, July 2007.
  4. T. Sakunkonchak, S. Komatsu, M. Fujita,
    "Synchronization Verification in System-Level Design with ILP Solvers,"
    IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E89-A, No. 12, pp.3387-3396, Dec. 2006.
  5. Y. Liu, S. Komatsu, M. Fujita,
    "The AMS Extension to System Level Design Language--SpecC,"
    IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E89-A, No. 12, pp.3397-3407, Dec. 2006.
  6. 西原 佑, 松本 剛史, 小松 聡, 藤田 昌宏,
    "状態遷移表現への変換に基づくハードウェア/ソフトウェア協調設計の形式的検証手法,"
    電子情報通信学会論文誌D Vol. J89-D, No. 4, pp. 651-659, 2006.
  7. Y. Liu, S. Komatsu, M. Fujita,
    "Synchronization Mechanism for Timed/Untimed Mixed-Signal System Level Design Environment,"
    IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E89-A, No. 4, pp. 1018-1026, 2006.
  8. S. Komatsu, M. Fujita,
    "Low Power and Fault Tolerant Encoding Methods for On-Chip Data Transfer in Practical Applications,"
    IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E88-A, No. 12, pp. 3282-3289, Dec. 2005.
  9. S. Komatsu. M. Fujita,
    "Irredundant Low Power Address Bus Encoding Techniques Based on Adaptive Codebooks,"
    IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E86-A, No. 12, pp.3001-3008, Dec. 2003.
  10. T. Sakunkonchak, S. Komatsu, M. Fujita,
    "Verification of Synchronization in SpecC Description with the Use of Difference Decision Diagrams,"
    IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E86-A, No. 12, pp.3192-3199, Dec. 2003.
  11. M. Miyama, O. Tooyama, N. Takamatsu, T. Kodake, K. Nakamura, A. Kato, J. Miyakoshi, K. Imamura, H. Hashimoto, S. Komatsu, M. Yagi, M. Morimoto, K. Taki, M. Yoshimoto,
    "An Ultra Low Power Motion Estimation Processor for MPEG2 HDTV Resolution Video,"
    IEICE Trans. on Electronics, Vol.E86-C, No.4, pp.561-569, Apr. 2003.
  12. K. Asada, M. Ikeda and S. Komatsu,
    "Approaches for Reducing Power Consumption in VLSI Bus Circuits,"
    IEICE Trans. on Electronics, Vol. E83-C, No. 2, pp.153-160, Feb. 2000.
  13. 浜田 玲子, 小松 聡, 池田 誠, 浅田 邦博,
    "マイクロプロセッサにおけるデータバス信号系列の統計的解析および疑似データ生成モデルの提案,"
    電子情報通信学会論文誌レター論文, Vol. J82-A, No. 8, pp. 1406-1408, 1999年8月.
  14. S. Komatsu, M. Ikeda, K. Asada,
    "Adaptive Codebook Encoding for Low-Power Chip Interface,"
    Electronics and Communications in Japan, Part 2: Electronics, Vol. 83, No. 1, pp. 17-24, 2000.
  15. 小松 聡, 池田 誠, 浅田 邦博,
    "適応型コード帳符号化による低消費電力チップインタフェースの検討,"
    電子情報通信学会論文誌, Vol. J82-C-II, No. 4, pp. 203-209, 1999年4月.

Book Chapter

  1. 「はかる×わかる半導体 入門編(日経BPコンサルティング, ISBN978-4-86443-039-5, 浅田邦博監修)」第4章半導体の試験項目を執筆, 2013年5月.
  2. M. Fujita, S. Komatsu, and H. Saito,
    "Dependable Computing Systems: Chapter 1 Formal Verification Techniques for Digital Systems,"
    Wiley-Interscience, pp.3-25, 2005.
  3. S. Komatsu, H. Saito, K. Seto, Y. Kojima, and M. Fujita,
    Chapter 14: Engineering Changes in Field Modifiable Architectures in "Formal Methods and Models for System Design -- A System Level Perspective --," (Editors: R. Gupta, P. Le Guernic,S.K. Shukla, J.P. Talpin)
    Kluwer Academic Publishers, (全374ページ, pp. 353-372 ), 2004.

Refereed International Conference/Symposium/Workshop

  1. James S. Tandon, Takahiro J. Yamaguchi, Satoshi Komatsu, and Kunihiro Asada,
    “A Stochastic Sampling Time-to-Digital Converter with Tunable 180-770fs Resolution, INL less than 0.6LSB, and Selectable Dynamic Range Offset,”
    accepted for publication in IEEE Custom Integrated Circuites Conference, 2013.
  2. Takahiro. J. Yamaguchi, James S. Tandon, Satoshi Komatsu, and Kunihiro Asada,
    “A Novel Test Structure for Measuring Variance of Threshold Voltage in MOSFETs,”
    accepted for publication in IEEE International Test Conference, 2013.
  3. Rimon Ikeno, Takashi Maruyama, Tetsuya Iizuka, Satoshi Komatsu, Makoto Ikeda, and Kunihiro Asada,
    “A structured routing architecture and its design methodology suitable for high-throughput electron beam direct writing with character projection method,"
    ACM International Symposium on Physical Design (ISPD 2013), pp. 69-76, March 26th, 2013.
  4. Takashi Maruyama, Hiroshi Takita, Rimon Ikeno, Morimi Osawa, Yoshinori Kojima, Shinji Sugatani, Hiromi Hoshino, Toshio Hino, Masaru Ito, Tetsuya Iizuka, Satoshi Komatsu, Makoto Ikeda, and Kunihiro Asada,
    “Practical proof of CP element based design for 14nm node and beyond,”
    SPIE2013 Advanced Lithography, 8680-75 (2013)
  5. Rimon Ikeno, Takashi Maruyama, Tetsuya Iizuka, Satoshi Komatsu, Makoto Ikeda, and Kunihiro Asada,
    “High-throughput Electron Beam Direct Writing of VIA Layers by Character Projection using Character Sets Based on One-dimensional VIA Arrays with Area-efficient Stencil Design,”
    18th Asia and South Pacific Design Automation Conference (ASP-DAC 2013), 3C-2, pp.255-260, Jan. 23rd, 2013.
  6. T. J. Yamaguchi, K. Asada, K. Niitsu, M. Abbas, S. Komatsu, H. Kobayashi, J. A. Moreira,
    “A New Procedure for Measuring High-Accuracy Probability Density Functions,”
    2012 IEEE Asian Test Symposium, pp. 185-190, November 2012.
  7. Masahiro Ishida, Toru Nakura, Toshiyuki Kikkawa, Takashi Kusaka, Sotoshi Komatsu and Kunihiro Asada,
    “Power Integrity Control of ATE for Emulating Power Supply Fluctuation on Customer Environment,”
    IEEE International Test Conference, November 2012.
  8. T. J. Yamaguchi, S. Komatsu, M. Abbas, K. Asada, N. Mai-Khanh, and J. Tandon,
    “A CMOS Flash TDC with 0.84-1.3ps Resolution Using Standard Cells,”
    2012 IEEE RFIC Symposium, pp. 527-530, Jun. 2012.
  9. M. Abbas, T. J. Yamaguchi, Y. Furukawa, S. Komatsu, K. Asada,
    "Low Delay Dispersion Comparator for Level-Crossing ADCs,"
    2012 Japan-Egypt Conference on Electronics, Communications and Computers, Mar. 2012
  10. M. Abbas, T. J. Yamaguchi, Y. Furukawa, S. Komatsu, K. Asada,
    "Novel technique for minimizing the comparator delay dispersion in 65nm CMOS technology,"
    18th IEEE International Conference on Electronics, Circuits and Systems (ICECS), pp. 220-223, Dec. 2011.
  11. T. Maruyama, S. Sugatani, Y. Machida, H. Takita, H. Hoshino, T. Hino, M. Ito, A. Yamada, T. Iizuka, S. Komatsu, M. Ikeda, K. Asada,
    “CP element-based design for 14nm node EBDW high-volume manufacturing,”
    2012 SPIE Advanced Lithography, 8323-39, Feb. 2012.
  12. T. J. Yamaguchi, M. Soma, T. Aoki, Y. Furukawa, K. Degawa, K. Asada, M. Abbas, S. Komatsu,
    "Application of a continuous-time level crossing quantization method for timing noise measurements,"
    2011 IEEE International Test Conference (ITC), Sep. 2011.
  13. T. J. Yamaguchi, M. Abbas, M. Soma, T. Aoki, Y. Furukawa, K. Degawa, S. Komatsu, and K. Asada,
    "An Equivalent-Time and Clocked Approach for Continuous-Time Quantization,"
    IEEE International Symposium on Circuits and Systems 2011 (ISCAS 2011), pp. 2529-2532, May. 2011.
  14. M. Abbas, Y. Furukawa, S. Komatsu, T. J. Yamaguchi, and K. Asada,
    “Clocked Comparator for High-Speed Applications in 65nm Technology,”
    IEEE Asian Solid-State Circuits Conference 2010 (A-SSCC2010), pp. 277-280, Nov. 2010.
  15. Mohamed Abbas, Tim Cheng, Yasuo Furukawa, Satoshi Komatsu and Kunihiro Asada, Design,
    “An Automatic Test Generation Framework for Digitally-Assisted Adaptive Equalizers in High-Speed Serial Links,”
    Automation & Test in Europe 2010 (DATE 2010), pp. 1755-1760, 2010.
  16. M. Abbas, Y. Furukawa, S. Komatsu, and K. Asada,
    “Signature-Based Testing for Adaptive Digitally-Calibrated Pipelined Analog-to-Digital Converters,”
    IEEE 8th International Conference on ASIC (ASICON2009), Oct. 2009.
  17. M. Abbas, K.T. Cheng, Y. Furukawa, S. Komatsu, and K. Asada,
    “GA-Based Test Generation for Digitally-Assisted Adaptive Equalizers in High-Speed Serial Links,”
    IEEE East-West Design & Test Symposium (EWDTS2009), pp. 287-292, Sep. 2009.
  18. M. Abbas, K. T. Cheng, Y. Furukawa, S. Komatsu, and K. Asada,
    “Signature-Based Testing for Digitally-Assisted Adaptive Equalizers in High-Speed Serial Links,”
    14th IEEE European Test Symposium (ETS’09), pp. 107-112, May 2009.
  19. G. Fey, S. Komatsu, Y. Furukawa, and M. Fujita,
    "Targeting Leakage Constraints during ATPG,"
    Proc. of 17th Asian Test Symposium (ATS’08), pp. 225-230, Nov. 2008.
  20. S. Komatsu,
    “VLSI Test Exercise Courses for Students in EE Department,”

    Proc. of 39th International Test Conference (ITC2009), PO. 10, Oct. 2008.
  21. G. Fey, S. Komatsu, Y. Furukawa, and M. Fujita,
    "Targeting Leakage Constraints during ATPG,"
    Proc. of 5th IEEE International Workshop on Silicon Debug and Diagnosis (SDD08), pp.225-230, Apr. 2008.
  22. T. Sakunkonchak, S. Komatsu, M. Fujita,
    "Using Counterexample Analysis to Minimize the Number of Predicates for Predicate Abstraction,"
    Proc. of 5th International Symposium on Automated Technology for Verification and Analysis, pp.553-563, Oct. 2007.
  23. T. Sakunkonchak, T. Matsumoto, H. Saito, S. Komatsu, and M. Fujita,
    "Equivalence Checking in C-based System-Level Design by Sequentializing Concurrent Behaviors,"
    Proc. of IASTED International Conference on Advances in Computer Science and Technology, pp.36-42, April 2007.
  24. S. Komatsu, K. Takagi, M. Fujita, K. Asada,
    “VLSI CAD Education and Exercise Course with Public Domain Tools,”
    IEEE International Conference on Microelectronic Systems Education (MSE07), pp. 111-112, Jun. 2007.
  25. Y. Lee, Y. Ishikawa, S. Kang, G. Park, S. Watanabe, K. Seto, S. Komatsu, H. Hamamura, M. Fujita,
    "UML-based Specification Method of Hardware IPs for Efficient IP Reuse,"
    Proc. of International UML-SoC Workshop at Design Automation Conference, pp.23-30, June 2007.
  26. S. Gao, K. Seto, S. Komatsu, M. Fujita,
    "Interconnect-aware Pipeline Synthesis for Array based Reconfigurable Architectures,"
    Proc. of International Embedded Systems Symposium 2007, pp.121-134, May 2007.
  27. S. Watanabe, K. Seto, Y. Ishikawa, S. Komatsu, M. Fujita,
    "Protocol Transducer Synthesis using Divide and Couquer Approach,"
    Asia and South Pacific Design Automation Conference, pp. 280-285, Jan. 2007.
  28. Shota Watanabe, Yuji Ishikawa, Kenshu Seto, Satoshi Komatsu and Masahiro Fujita,
    "Dynamically Reconfigurable Protocol Transducer,"
    Proceedings of the International Conference on Field Programmable Technology (ICFPT06), pp. 341-344, Dec. 2006.
  29. Shota Watanabe, Kenshu Seto, Yuji Ishikawa, Satoshi Komatsu, Masahiro Fujita,
    "Automatic Protocol Transducer Synthesis aiming at facilitating IP-Reuse,"
    Proceedings of International Workshop on Logic and Synthesis (IWLS2006), pp. 164-170, Jun. 2006.
  30. S. Komatsu, M. Ikeda, K. Asada,
    "A New Trial on VLSI Test Exercise Course for Undergraduate/Graduate School in EE Department,"
    6th International Workshop on Microelectronics Education, pp. 92-95, Jun. 2006.
  31. S. Komatsu, M. Fujita,
    "An Optimization of Bus Interconnects Pitch for Low-Power and Reliable Bus Encoding Scheme,"
    2006 IEEE International Symposium on Circuits and Systems, pp. 1723-1726, May 2006.
  32. S. Gao, K. Seto, S. Komatsu, M. Fujita,
    "Pipeline scheduling for array based reconfigurable architectures considering interconnect delays,"
    4th IEEE International Conference on Field Programmable Technologies, pp 137-144, Dec. 2005.
  33. Y. Liu, S. Komatsu, M. Fujita,
    "AMS Extensions for Timed/Untimed System Level Design Language,"
    FDL'05, pp. 77-80, Sep.27-30 2005, Lausanne, Switzerland.
  34. Thanyapat Sakunkonchak, Satoshi Komatsu, Masahiro Fujita
    "Synchronization Verification in System-Level Design with ILP Solver,"
    In 3rd ACM-IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE 2005), Verona, Italy, July 2005.
  35. Y. Liu, T. Sakunkonchak, S. Komatsu, M. Fujita,
    "System Level Design Language Extensions for Timed/Untimed Digital-Analog Combined System Design,"
    GLSVLSI, pp. 130-133, Mar. 2005, Chicago, U.S.
  36. Satoshi Komatsu and Masahiro Fujita,
    "Low Power and Fault Tolerant Encoding Methods for On-Chip Data Transfer,"
    The 12th Workshop on Synthesis And System Integration of Mixed Information Technologies, pp. 34-40, Oct. 2004.
  37. Y. Mita, S. Komatsu, M. Ikeda, M. Fujishima, K. Asada,
    "Practical Course of Design, Fabrication and Testing of CMOS Gate Array,"
    5th European Workshop on Microelectronics Education, Apr. 2004.
  38. M. Fujita, S. Komatsu, T. Sakunkonchak, Y. Kojima, K. Tanabe, and T. Matsumoto,
    "CAD Techniques for Hardware/Software Co-design Targeting Space Satellites,"

    Proc. of International Symposium on Electronics for Future Generations, pp. 107-112, Mar. 2004.
  39. S. Komatsu,
    "Research and Education Activities of VDEC (VLSI Design and Education Center),"
    Waseda University System LSI International Workshop, Jan. 2004.
  40. Tohru Ishihara, Satoshi Komatsu, Makoto Ikeda, Masahiro Fujita, Kunihiro Asada,
    "Comparative study on Verilog-based and C-based hardware design education,"
    2003 International Conference on Microelectronic Systems Education, Jun. 2003.
  41. H. Saito, K. Seto, Y. Kojima, S. Komatsu, and M. Fujita,
    "Engineering Changes in Field Modifiable Architectures,"
    Proc. of International Conference on Formal Methods and Models for Co-Desgn, pp. 87-94, Jun. 2003.
  42. S. Komatsu and M. Fujita,
    "Irredundant Address Bus Encoding Techniques based on Adaptive Codebooks for Low Power,"
    Proc. Asia South Pacific Design Automation Conference, pp.9-14, Jan. 2003.
  43. M. Fujita, S. Komatsu, H. Saito, K. Seto, T. Sakunkonchak, and Y. Kojima,
    "Field Modifiable Architecture with FPGAs and its Design/Verification/Debugging Methodologies,"
    Proc. of Annual Hawaii International Conference on System Sciences, pp. 279, Jan. 2003.
  44. S. Komatsu, Y. Kojima, H. Saito, K. Seto, and M. Fujita,
    "Field Modifiable Architecture with FPGAs and its Design Methodology,"
    Proc. of IEEE International Conference on Field-Programmable Technology, pp. 382-385, Dec. 2002.
  45. K. Seto, Y. Kojima, H. Saito, S. Komatsu, and M. Fujita,
    "Field Modifiable Architecture and its Design Method,"
    ACM SIGPLAN Conference on Programming Language Design and Implementation, 2002.
  46. Y. Kojima, H. Saito, K. Seto, S. Komatsu and M. Fujita,
    "Field Modifiable Architecture and Its Design Methodology -System Design Without Logic Synthesis-,"
    Proc. of IEEE/ACM International Workshop on Logic and Synthesis, pp. 103-108, Jun. 2002.
  47. M. Miyama, O. Tooyama, N. Takamatsu, T. Kodake, K. Nakamura, A. Kato, J. Miyakoshi, K. Imamura, H. Hashimoto, S. Komatsu, M. Yagi, M. Morimoto, K. Taki and M. Yoshimoto,
    "An Ultra Low Power, Realtime MPEG2 MP@HL Motion Estimation Processor Core with SIMD Datapath Architecture Optimized for Gradient Descent Search Algorithm,"
    IEEE 2002 Custom Integrated Circuits Conference, Florida, USA (2002.5), Proc. IEEE Custom Integ. Conf., pp. 167-170 2002.
  48. T. Ishihara, S. Komatsu, K. Asada,
    "An Inter-University Joint Program for a Trial of IP-Based System LSI Design,"
    4th European Workshop on Microelectronics Education, May 2002.
  49. S. Komatsu, M. Ikeda, and K. Asada,
    "Bus Data Encoding with Coupling-driven Adaptive Code-book Method for Low Power Data Transmission,"
    Proc. of European Solid-State Circuits Conference, pp. 312-315, Sep. 2001.
  50. S. Komatsu, M. Ikeda and K. Asada,
    "Bus Data Encoding with Adaptive Code-book Method for Low Power IP Based Design,"
    International Workshop on IP-Based Synthesis and SoC Design, pp. 77-81, Dec. 2000. (Best IP/SoC Prize)
  51. K. Asada, S. Komatsu, and M. Ikeda,
    "Associative Memory with Minimum Hamming Distance Detector and its Application to Bus Data,"
    Proc. of AP-AS 99, pp.16.1, Aug. 1999.
  52. S. Komatsu, M. Ikeda and K. Asada,
    "Low Power Chip Interface Based on Bus Data Encoding with Adaptive Code-Book Method,"
    9th Great Lakes Symposium on VLSI, 9B.1, pp. 368-371, Mar. 1999.
  53. S. Komatsu, M. Ikeda and K. Asada,
    "Low Power Microprocessors for Comparative Study on Bus Architecture and Multiplexer Architecture,"
    Asia and South Pacific Design Automation Conference 1998, 5D.3P, pp. 323-324, Feb. 1998.

Domestic Conference/Symposium/Workshop

  1. 小松 聡, Mohamed Abbas, 古川靖夫, 浅田邦博,
    “(招待講演)ディジタルアシストアナログ回路向けの自動テスト生成フレームワーク,”
    信学技報, vol. 110, no. 210, VLD2010-46, pp. 25-30, 2010年9月.
  2. 石川悠司, 小松聡, 藤田昌宏,
    "積グラフ探索を利用した実用的なプロトコル変換器の自動合成と検証,"
    電子情報通信学会技術研究報告, Vol.107, No.506, pp.1-6, 2008年3月.
  3. 石川悠司, 小松聡, 藤田昌宏,
    "IP 再利用のための動的再構成可能プロトコル変換器合成手法,"
    電子情報通信学会技術研究報告, Vol.107, No.225, pp.53-58, 2007年9月.
  4. 石川悠司, 小松聡, 藤田昌宏,
    "IP 再利用のためのプロトコル変換器自動合成,"
    第9回組込みシステム技術に関するサマーワークショップ(SWEST9), pp.92-95, 2007年8月.
  5. 石川 悠司, SeongWoon Kang, 李 蓮福, GiLark Park, 渡邊 翔太, 瀬戸 謙修, 小松 聡, 浜村 博史, 藤田 昌宏
    "ハードウェア設計における設計資産の仕様記述およびその検証手法,"
    電子情報通信学会技術研究報告, Vol. 106, No.547, pp. 43-48, 2007年3月.
  6. 李蓮福, GiLark Park, 石川悠司, SeongWoon Kang, 渡邊翔太, 瀬戸謙修, 小松聡, 浜村博史, 藤田昌宏
    "設計再利用のためのIPライブラリ検索システム,"
    電子情報通信学会技術研究報告, Vol. 106, No.547, pp. 49-54, 2007年3月.
  7. 渡辺 翔太, 瀬戸 謙修, 石川 悠司, 小松 聡, 藤田 昌宏,
    "設計再利用の為のプロトコル変換器合成手法,"
    第19回 回路とシステム軽井沢ワークショップ, pp. 229-234, Apr 2006.
  8. 松本剛史, 小松聡, 藤田昌宏,
    "動作合成前後の設計記述に対する記号シミュレーションによる形式的等価性検証の検討,"
    電子情報通信学会技術研究報告, Vol.106, No.32, pp.7-12, 2006年5月.
  9. 松本剛史, Thanyapat Sakunkonchak, 齋藤寛, 小松聡, 藤田昌宏,
    "線形計画法を利用したシステムレベル設計での動作並列化前後での等価性検証手法,"
    DAシンポジウム論文集, pp.157-162, 2006年7月.
  10. 松井健, 小松聡, 藤田昌宏,
    "組込みシステムのシステムレベル設計におけるオブジェクト指向技術の応用,"
    電子情報通信学会技術研究報告, 2006年3月.
  11. S. Gao, Y. Ishikawa, S. Watanabe, K. Seto, S. Komatsu, M. Fujita,
    "Pipeline Synthesis for Array Based Reconfigurable Architectures Considering Interconnect Delays,"
    DAシンポジウム2005, pp. 225-230, 2005年8月.
  12. Y. Liu, S. Komatsu, M. Fujita,
    "Timed/Untimed Synchronization for Mixed-Signal System Level Design Environment,"
    18th Workshop on Circuits and Systems in Karuizawa, Apr.2005, Karuizawa, Japan.
  13. 松井健, 小松聡, 藤田昌宏,
    "UMLとSpecCを用いたハードウェアの上位設計手法に関する検討,"
    電子情報通信学会技術研究報告 VLD2004-136, pp.65-70, 2005年3月.
  14. Thanyapat Sakunkonchak, Satoshi Komatsu, Masahiro Fujita,
    "A Framework on Synchronization Verification of System-Level Design,"
    電子情報通信学会技術研究報告 Vol.104, No.708, pp.71-76, 2005年3月.
  15. 小松聡, 藤田昌宏,
    "データ符号化によるVLSIにおける低消費電力・高信頼データ伝送手法の検討,"
    電子情報通信学会技術研究報告 Vol. 104, No. 478, VLD2004-92, pp. 185-190, 2004年12月.
  16. 松井 健, 小松 聡, 藤田 昌宏,
    "UML を用いた実時間・高信頼性組み込みシステムの上位設計についての検討,"
    電子情報通信学会技術研究報告 Vol. 103, No. 735, pp. 33-38, 2004 年 3 月.
  17. 佐々木 俊介, 小松 聡, 藤田 昌宏,
    "電子系・機械系協調設計における設計検証法に関する検討,"
    電子情報通信学会技術研究報告 Vol. 103, No, 735, pp. 27-32, 2004 年 3 月.
  18. 田辺 健, 齋藤 寛, 小松 聡, 藤田 昌宏,
    "SpecC 言語によるハードウェア・ソフトウェア混在システム記述を対象としたプログラムスライシング手法の提案,"
    電子情報通信学会技術研究報告 Vol. 103, No. 702, pp. 79-84, 2004 年 3 月.
  19. 小島 慶久, 瀬戸 謙修, 齋藤 寛, 小松 聡, 藤田 昌宏,
    "リコンフィギャラブルなブロック間接続をもつアーキテクチャの静的最適化のための高位合成手法,"
    電子情報通信学会第 2 種研究会 (第 2 回リコンフィギャラブルシステム研究会)技術研究報告, pp. 16-21, 2003 年 11 月.
  20. 小松 聡, 藤田 昌宏,
    "LSI における検証技術,"
    ソフトウェア工学の基礎ワークショップ, pp. 251-256, 2003 年 11 月.
  21. 小松 聡, 石原 亨, 藤田 昌宏,
    "Cプログラムからのハードウェア設計教育 --Handel-C と DK1 を使った演習--."
    DA シンポジウム, pp. 253-258, 2003 年 7 月.
  22. 小松 聡, 藤田 昌宏,
    "低電力設計のための非冗長アドレスバス符号化手法の提案,"
    DA シンポジウム, pp. 167-172, 2002 年 7 月.
  23. 劉 宇, 世羅 元啓, 小松 聡, 藤田 昌宏,
    "Integration of Logic Optimization and Layout Processes by Using Rewriting Method,"
    DA シンポジウム, pp. 217-222, 2002 年 7 月.
  24. 中村 毎良, 深山 正幸, 遠山 治, 高松 直樹, 小竹 剛, 加藤 藍, 宮越 純一, 今村 幸祐, 橋本 秀雄, 小松 聡, 八木 幹雄, 森本 薫夫, 瀧 和男, 吉本 雅彦,
    "HDTV対応低消費電力MPEG2/MP@HL動き検出プロセッサLSIの開発,"
    電子情報通信学会集積回路研究会、金沢(2002.5), 研究会予稿集, 2002.
  25. 小松 聡, 池田 誠, 浅田 邦博,
    "低消費電力データ転送のための配線間結合容量を考慮した適応型コード帳符号化方式の提案と評価,"
    DA シンポジウム, pp. 101-106, 2001 年 7 月.
  26. 小松 聡, 池田 誠, 浅田 邦博,
    "高スループットデータ伝送のための圧縮符号化手法の提案と評価,"
    第4回システムLSI琵琶湖ワークショップ, pp. 215-218, 2000年11月.
  27. 小松 聡, 池田 誠, 浅田 邦博,
    "低消費電力チップインタフェースのための適応型コード帳符号化方式の回路評価,"
    電子情報通信学会総合大会, C12-14, p. 109, 2000年3月.
  28. 小松 聡, 池田 誠, 浅田 邦博,
    "適応型コード帳符号化を用いた低消費電力チップインタフェース,"
    信学技報, DSP98-89, ICD98-176, CPSY98-91, pp. 1-6, 1998年10月.
  29. 小松 聡, 池田 誠, 浅田 邦博,
    "低消費電力チップインタフェースのための適応型コード帳符号化方式,"
    電子情報通信学会ソサイエティ大会, C12-23, p. 114, 1998年9月.
  30. 小松 聡, 池田 誠, 浅田 邦博,
    "バス方式とマルチプレクサ方式の比較によるマイクロプロセッサの低消費電力化への検討,"
    第1回システムLSI琵琶湖ワークショップ, pp. 395-399, 1997年11月.
  31. 小松 聡, 池田 誠, 浅田 邦博,
    "動的コード帳符号化によるチップインタフェースにおける消費電力削減手法の検討,"
    信学技報, DSP97-97, SDM97-135, ICD97-151, pp. 9-14, 1997年10月.
  32. 小松 聡, 池田 誠, 浅田 邦博,
    "低消費電力マイクロプロセッサにおけるマルチプレクサ方式とバス方式の比較検討,"
    電子情報通信学会ソサイエティ大会, C12-16, p. 99, 1997年9月.
  33. 小松 聡, 池田 誠, 浅田 邦博,
    "低電力マイクロプロセッサにおけるマルチプレクサ方式とバス方式の比較検討,"
    電子情報通信学会総合大会, C-12-46, p. 182, 1997年3月.
  34. 小松 聡, 池野 理門, 伊藤 浩, 浅田 邦博,
    "DTMOSのドレイン電流特性のデザインパラメ-タ依存性とその最適化,"
    信学技報VLD96-43, pp. 17-22, 1996年9月.
  35. 小松 聡, 池野 理門, 伊藤 浩, 浅田 邦博,
    "DTMOSのドレイン電流特性のデザインパラメ-タ依存性,"
    第43回応用物理学会関係連合講演会, 26p-H-4, p. 1335, 1996年3月.

Awards

  1. International Workshop on IP-Based Synthesis and SoC Design Best IP/SoC Prize 2000.
  2. Best Paper Award, 12th Asia and South Pacific Design Automation Conference (ASP-DAC 2007) (co-author)
  3. Best Paper Award, 2012 Japan-Egypt Conference on Electronics, Communications and Computers (co-author)

特許

(登録済)

  1. 古川 靖夫, Goerschwin Fey, 小松 聡, 藤田 昌宏, 「Test Apparatus, Test Method and Recording Medium」, 台湾特許第I392887号(2013/4/11).
  2. 古川 靖夫, Goerschwin Fey, 小松 聡, 藤田 昌宏, 「(日本語訳)試験装置、試験方法及び記録媒体」, 韓国特許第10-1187065号(2012/9/24).
  3. Yasuo Furukawa, Goerschwin Fey, Satoshi Komatsu, Masahiro Fujita, “Test Appartus, Test Method, Program, and Recording Medium Reducing the Influence of Variations,” United States patent no. US 8,185,336 (2012/5/22).
  4. Yasuo Furukawa, Goerschwin Fey, Satoshi Komatsu, Masahiro Fujita, “Test apparatus, test vector generate unit, test method, program, and recording medium,” United States patent no. US 7,984,353 (2011/7/19).

(審査請求中)

  1. 古川 靖夫, ゲルシュウィン フェイ, 小松 聡, 藤田 昌宏, 「試験装置、試験方法、および、プログラム」, 特願2009-241875号(2009/10/20), 特開2010-107507号(2010/5/13).

(公開中)

  1. 石田 雅裕, 浅田 邦博, 名倉 徹, 小松 聡, 「試験装置」, 特願2011-226132号(2011/10/13), 特開2013-88146号(2013/5/13).
  2. 古川 靖夫, モハメド アッバス, 小松 聡, 「コンパレータ回路およびそれを用いた試験装置」, 特願2010-185020号(2010/8/20), 特開2012-44521号(2012/3/1).

(出願中)

  1. 石田 雅裕,日下 崇,名倉 徹,小松 聡,吉川 俊之,浅田 邦博,「電源装置,それを用いた試験装置,電源電圧の制御方法」, 特願2012-221619(2012/10/3).
  2. 石田 雅裕,名倉 徹,小松 聡,浅田 邦博,「試験装置および試験条件の取得方法」,特願2012-221620号(2012/10/3).
  3. 「ロジックセルのCPクラスタ方法」, 特願2012-006589 (2012/01/16)
  4. 「ロジックセルのCP変換方法」, 特願2012-006588 (2012/01/16)
  5. 「構造化配線/VIA構成方法」, 特願2013-011506 (2013/01/24)

Last Updated: May. 21, 2013.