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List of Publications

 

Book Chapter

  1. Verification of Synchronization in SpecC Description with the Use of Difference Decision Diagrams
    Thanyapat Sakunkonchak and Masahiro Fujita
    In System Specification and Design Languages: Best of FDL'02 Ed. By Eugenio Villar and Jean P. Mermet
    Kluwer Academic Publisher, April 2003, ISBN 1-4020-7414-X.


International Journal

  1. Dependence Graph Based Verification and Synthesis of Hardware/Software Co-Designs with SAT Related Formulation (Online)
    Masahiro Fujita, Kenshu Seto, and Thanyapat Sakunkonchak
    In Journal on Satisfiability, Boolean Modeling and Computation
    Special Volume on Application of Constraints to Formal Verification. Editor: Miroslav Velev
    Vol.5 (2008), pp.57--82.

  2. Synchronization Verification in System-Level Design with ILP Solvers (Online)
    Thanyapat Sakunkonchak, Satoshi Komatsu and Masahiro Fujita
    In IEICE Trans. on Special Section on VLSI Design and CAD Algorithms, Vol.E89--A, No.12, pp.3387--3396, December 2006.

  3. Verification of Synchronization in SpecC Descriptions with the Use of Difference Decision Diagrams (Online)
    Thanyapat Sakunkonchak, Satoshi Komatsu and Masahiro Fujita
    In IEICE Trans. on Special Section on VLSI Design and CAD Algorithms, Vol.E86--A, No.12, pp.3192--3199, December 2003.

  4. A high-speed multiplier-free realization of IIR filter using ROM's and elevated signal rate (Online)
    Thanyapat Sakunkonchak and Sawasd Tantaratana
    In IEICE Trans. on Fundamentals, Vol.E84--A, No.6, pp. 1479--1487, June 2001.


International Conference

  1. Using Counterexample Analysis to Minimize the Number of Predicates for Predicate Abstraction (PDF)(PPT)
    Thanyapat Sakunkonchak, Satoshi Komatsu, and Masahiro Fujita
    In The 5th International Symposium on Automated Technology for Verification and Analysis (ATVA2007)
    pp.553--563, Tokyo, Japan, October 22-25 2007.

  2. Equivalence Checking in C-based System-Level Design by Sequentializing Concurrent Behaviors (PDF)(PPT)
    Thanyapat Sakunkonchak, Takeshi Matsumoto, Hiroshi Saito, Satoshi Komatsu, and Masahiro Fujita
    In The 3rd IASTED International Conference on Advances in Computer Science and Technology (ACST2007)
    pp.36--42, Phuket, Thailand, April 2-4 2007.

  3. Synchronization Verification in System-Level Design with ILP Solvers (PDF)(PPT)
    Thanyapat Sakunkonchak and Masahiro Fujita
    In Third ACM-IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE2005)
    pp.121--130, Verona Italy, July 11-14 2005.

  4. System Level Design Language Extensions for Timed/Untimed Digital-Analog Combined System Design (PDF)
    Yu Liu, Thanyapat Sakunkonchak, Satoshi Komatsu and Masahiro Fujita
    In Proc. of ACM Great Lakes Symposium on VLSI (GLSVLSI2005)
    pp.130--133, Chicago, USA, March 2005.

  5. CAD Techniques for Hardware/Software Co-design Targeting Space Satellites (PDF)
    Masahiro Fujita, Satoshi Komatsu, Thanyapat Sakunkonchak, Yoshihisa Kojima, Ken Tanabe and Takeshi Matsumoto
    In Proc. of International Symposium on Electronics for Future Generations
    pp.107--112, Tokyo Japan, March 2004.

  6. Formal Verification of Synchronization Issue in System-Level Design with Automatic Abstraction (PDF)(Poster)
    Thanyapat Sakunkonchak and Masahiro Fujita
    In IFIP International Conference on Very Large Scale Integration (IFIP VLSI-SoC 2003)
    pp.464, Darmstadt Germany, December 2003 (Ph.D. Forum).

  7. Formal Verification of Synchronization Issues in SpecC Description with Automatic Abstraction (PDF)(PPT)
    Thanyapat Sakunkonchak and Masahiro Fujita
    In Model Checking for Dependable Software-Intensive Systems Workshop
    In The International Conference on Dependable Systems and Networks (DSN-2003)
    pp.w67--w71, San Francisco USA, June 2003.

  8. Verification of Behavioral Consistency in C by Using Symbolic Simulation and Program Slicer (PDF)(PPT)
    Takeshi Matsumoto, Thanyapat Sakunkonchak, Hiroshi Saito, and Masahiro Fujita
    In Model Checking for Dependable Software-Intensive Systems Workshop
    In The International Conference on Dependable Systems and Networks (DSN-2003)
    pp.w80--w84, San Francisco USA, June 2003.

  9. Field Modifiable Architecture with FPGAs and its Design/Verification/Debugging Methodologies (PDF)
    Masahiro Fujita, Satoshi Komatsu, Hiroshi Saito, Kenshu Seto, Thanyapat Sakunkonchak, and Yoshihisa Kojima
    In Proc. Hawaian International Conference on System Sciences (HICSS)
    pp.279--288, Hawai, January 2003.

  10. Formal Verification of Synchronization Issues in SpecC Description with Automatic Abstraction (PDF)(PPT)
    Thanyapat Sakunkonchak and Masahiro Fujita
    In The 22nd IFIP International Conference on Formal Techniques for Networked and Distributed Systems (FORTE 2002)
    pp.369, Houston USA, November 2002 (Poster Presentation).

  11. An Equivalence Checking Methodology for Hardware Oriented C-based Specifications (PDF)
    Hiroshi Saito, Takaya Ogawa, Thanyapat Sakunkonchak, Masahiro Fujita, and Takashi Nanya
    In Proc. IEEE International High Level Design Validation and Test Workshop (HLDVT)
    pp.139--144, October 2002.

  12. Verification of Synchronization in SpecC Description with the Use of Difference Decision Diagrams (PDF)(PPT)
    Thanyapat Sakunkonchak and Masahiro Fujita
    In Forum on specification & Design Languages (FDL'02)
    Marseille France, September 2002.

  13. A High-Speed Multiplier-Free Realization of IIR Filter Using ROM's (PDF)
    Thanyapat Sakunkonchak and Sawasd Tantaratana
    In Proc. of International Technical Conference & Circuits, Systems, Computers and Communications 2000 (ITC-CSCC2000)
    pp.711--714, Pusan Korea, July 2000.

  14. A Pipelined Multiplier-Free Realization of IIR Filter Using ROM's and Periodically Time-Varying Structure (PDF)
    Thanyapat Sakunkonchak and Sawasd Tantaratana
    In Proc. of IEEE International Symposium on Intelligent Signal Processing and Communication Systems (ISPAC'99)
    pp.597--600, Phuket Thailand, December 1999.


Local Journal/Conference

  1. An Equivalence Checking Method for System-Level Designs Under Different Schedulings Applying Sequentialization with ILP Solvers (PDF)(PPT)
    Takeshi Matsumoto, Thanyapat Sakunkonchak, Hiroshi Saito, Satoshi Komatsu and Masahiro Fujita
    In DA Symposium 2006
    pp.157--162, Hamamatsu Japan, July 2006.

  2. A Framework on Synchronization Verification in System-Level Design (PDF)(PPT)
    Thanyapat Sakunkonchak, Satoshi Komatsu and Masahiro Fujita
    In IEICE Technical Research Report on VLSI Design Technology (VLD2005)
    Vol.104, No.708, pp.71--76, Okinawa Japan, March 2005.

  3. Verification of Synchronization in SpecC Descriptions Using Difference Decision Diagram (PDF)(PPT)
    Thanyapat Sakunkonchak and Masahiro Fujita
    In DA Symposium 2002
    pp.137--142, Hamamatsu Japan, July 2002.

  4. Implementation of ROM-Based Multiplier-Free Realization of IIR Filters
    Thanyapat Sakunkonchak and Sawasd Tantaratana
    In The 22nd Annual National Conference on Electronics, High Performance Computing, Telecommunication and Information (ECTI-22)
    Bangkok, Thailand, June, 2001.

  5. A High-Speed Multiplier-Free Realization of IIR Filter Using ROM'S
    Thanyapat Sakunkonchak and Sawasd Tantaratana
    In NECTEC (Thailand) Technical Journal
    Vol.II, No.7, March-June, 2000.